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<title>user/sven/linux.git/include/drm/drm_cache.h, branch v4.18-rc2</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v4.18-rc2</id>
<link rel='self' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v4.18-rc2'/>
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<updated>2018-02-13T16:57:59Z</updated>
<entry>
<title>drm: add func to get max iomem address v2</title>
<updated>2018-02-13T16:57:59Z</updated>
<author>
<name>Chunming Zhou</name>
<email>david1.zhou@amd.com</email>
</author>
<published>2018-02-09T02:44:08Z</published>
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<id>urn:sha1:82626363a217d79128c447ab296777b461e9f050</id>
<content type='text'>
it will be used to check if the driver needs swiotlb
v2: Don't use inline, instead, move function to drm_memory.c (Michel Daenzer &lt;michel@daenzer.net&gt;)

Signed-off-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Reviewed-by: Monk Liu &lt;monk.liu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Michel Dänzer &lt;michel.daenzer@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20180209024410.1469-1-david1.zhou@amd.com
</content>
</entry>
<entry>
<title>drm: Move drm_clflush prototypes to drm_cache header file</title>
<updated>2017-01-10T10:17:01Z</updated>
<author>
<name>Gabriel Krisman Bertazi</name>
<email>krisman@collabora.co.uk</email>
</author>
<published>2017-01-09T21:56:49Z</published>
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<id>urn:sha1:f9a87bd7d5b64075af87345ae42f3984c56bddb6</id>
<content type='text'>
Continue to clean up drmP.h by moving the cache flushing functions into
it's own header file.

Compile-tested only

Signed-off-by: Gabriel Krisman Bertazi &lt;krisman@collabora.co.uk&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
Link: http://patchwork.freedesktop.org/patch/msgid/20170109215649.6860-2-krisman@collabora.co.uk
</content>
</entry>
<entry>
<title>drm: Loongson-3 doesn't fully support wc memory</title>
<updated>2016-04-22T00:24:11Z</updated>
<author>
<name>Huacai Chen</name>
<email>chenhc@lemote.com</email>
</author>
<published>2016-04-19T11:19:11Z</published>
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<id>urn:sha1:221004c66a58949a0f25c937a6789c0839feb530</id>
<content type='text'>
Signed-off-by: Huacai Chen &lt;chenhc@lemote.com&gt;
Cc: stable@vger.kernel.org
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Dave Airlie &lt;airlied@redhat.com&gt;
</content>
</entry>
<entry>
<title>drm: add helper to check for wc memory support</title>
<updated>2016-02-02T15:08:43Z</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2016-01-30T05:59:32Z</published>
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<id>urn:sha1:4b0e4e4af6c6dc8354dcb72182d52c1bc55f12fc</id>
<content type='text'>
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Michel Dänzer &lt;michel.daenzer@amd.com&gt;
Signed-off-by: Dave Airlie &lt;airlied@redhat.com&gt;
Signed-off-by: Oded Gabbay &lt;oded.gabbay@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/ttm: consolidate cache flushing code in one place.</title>
<updated>2009-08-26T23:53:47Z</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2009-08-26T23:53:47Z</published>
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<id>urn:sha1:c9c97b8c75019814d8c007059bc827bb475be917</id>
<content type='text'>
This merges the TTM and drm cache flushing into one file in the
drm core.

Signed-off-by: Dave Airlie &lt;airlied@redhat.com&gt;
</content>
</entry>
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