<feed xmlns='http://www.w3.org/2005/Atom'>
<title>user/sven/linux.git/include/drm/intel, branch v6.17</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v6.17</id>
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<updated>2025-07-04T13:55:51Z</updated>
<entry>
<title>drm/xe/bmg: Add one additional PCI ID</title>
<updated>2025-07-04T13:55:51Z</updated>
<author>
<name>Vodapalli, Ravi Kumar</name>
<email>ravi.kumar.vodapalli@intel.com</email>
</author>
<published>2025-07-04T10:35:27Z</published>
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<id>urn:sha1:ccfb15b8158c11a8304204aeac354c7b1cfb18a3</id>
<content type='text'>
One additional PCI ID is added in Bspec for BMG, Add it so that
driver recognizes this device with this new ID.

Bspec: 68090
Cc: stable@vger.kernel.org # v6.12+
Signed-off-by: Vodapalli, Ravi Kumar &lt;ravi.kumar.vodapalli@intel.com&gt;
Reviewed-by: Shekhar Chauhan &lt;shekhar.chauhan@intel.com&gt;
Acked-by: Matthew Auld &lt;matthew.auld@intel.com&gt;
Signed-off-by: Matthew Auld &lt;matthew.auld@intel.com&gt;
Link: https://lore.kernel.org/r/20250704103527.100178-1-ravi.kumar.vodapalli@intel.com
</content>
</entry>
<entry>
<title>drm/xe: Add Wildcat Lake device IDs to PTL list</title>
<updated>2025-06-18T22:42:44Z</updated>
<author>
<name>Matt Roper</name>
<email>matthew.d.roper@intel.com</email>
</author>
<published>2025-06-13T19:31:43Z</published>
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<id>urn:sha1:3c0f211bc8fc0d0a0b4c29c471b57ffff48eec60</id>
<content type='text'>
Introduce wildcat lake device Id.
Wildcat Lake uses slightly different graphics and media IP versions
than Panther Lake, but can still be treated as PTL for general driver
flows.

Bspec: 73951
Signed-off-by: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Signed-off-by: Dnyaneshwar Bhadane &lt;dnyaneshwar.bhadane@intel.com&gt;
Reviewed-by: Tejas Upadhyay &lt;tejas.upadhyay@intel.com&gt;
Link: https://lore.kernel.org/r/20250613193146.3549862-7-dnyaneshwar.bhadane@intel.com
</content>
</entry>
<entry>
<title>drm/xe/xe2_hpg: Add PCI IDs for xe2_hpg</title>
<updated>2025-06-11T14:29:47Z</updated>
<author>
<name>Shekhar Chauhan</name>
<email>shekhar.chauhan@intel.com</email>
</author>
<published>2025-06-05T19:08:02Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=9b779ff0e1d1fa8a4e7d90405bcb902a1d5f4fe6'/>
<id>urn:sha1:9b779ff0e1d1fa8a4e7d90405bcb902a1d5f4fe6</id>
<content type='text'>
As per updated Bspec, Sync PCI IDs for BMG.

Bspec: 68090
Signed-off-by: Shekhar Chauhan &lt;shekhar.chauhan@intel.com&gt;
Signed-off-by: Dnyaneshwar Bhadane &lt;dnyaneshwar.bhadane@intel.com&gt;
Reviewed-by: Tejas Upadhyay &lt;tejas.upadhyay@intel.com&gt;
Reviewed-by: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Signed-off-by: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Link: https://lore.kernel.org/r/20250605190804.1287289-2-dnyaneshwar.bhadane@intel.com
</content>
</entry>
<entry>
<title>drm/xe/ptl: Update the PTL pci id table</title>
<updated>2025-05-21T20:48:25Z</updated>
<author>
<name>Matt Atwood</name>
<email>matthew.s.atwood@intel.com</email>
</author>
<published>2025-05-20T19:57:49Z</published>
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<id>urn:sha1:49c6dc74b5968885f421f9f1b45eb4890b955870</id>
<content type='text'>
Update to current bspec table.

Bspec: 72574

Signed-off-by: Matt Atwood &lt;matthew.s.atwood@intel.com&gt;
Reviewed-by: Tejas Upadhyay &lt;tejas.upadhyay@intel.com&gt;
Reviewed-by: Clint Taylor &lt;Clinton.A.Taylor@intel.com&gt;
Link: https://lore.kernel.org/r/20250520195749.371748-1-matthew.s.atwood@intel.com
Signed-off-by: Matt Roper &lt;matthew.d.roper@intel.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'drm-intel-next-2025-04-11' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next</title>
<updated>2025-04-14T19:06:51Z</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2025-04-14T19:06:46Z</published>
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<id>urn:sha1:b60301774a8fe6c30b14a95104ec099290a2e904</id>
<content type='text'>
Cross-subsystem Changes:
- Update GVT MAINTAINERS (Jani)

Driver Changes:
- Updates for xe3lpd display (Gustavo)
- Fix link training interrupted by HPD pulse (Imre)
- Watermark bound checks for DSC (Ankit)
- VRR Refactor and other fixes and improvements (Ankit)
- More conversions towards intel_display struct (Gustavo, Jani)
- Other clean-up patches towards a display separation (Jani)
- Maintain asciibetical order for HAS_* macros (Ankit)
- Fixes around probe/initialization (Janusz)
- Fix build and doc build issue (Yue, Rodrigo)
- DSI related fixes (Suraj, William, Jani)
- Improve DC6 entry counter (Mohammed)
- Fix xe2hpd memory type identification (Vivek)
- PSR related fixes and improvements (Animesh, Jouni)
- DP MST related fixes and improvements (Imre)
- Fix scanline_offset for LNL+/BMG+ (Ville)
- Some gvt related fixes and changes (Ville, Jani)
- Some PLL code adjustment (Ville)
- Display wa addition (Vinod)
- DRAM type logging (Lucas)
- Pimp the initial FB readout (Ville)
- Some sagv/bw cleanup (Ville)
- Remove i915_display_capabilities debugfs entry (Jani)
- Move PCH type to display caps debugfs entry (Jani)

Signed-off-by: Dave Airlie &lt;airlied@redhat.com&gt;

From: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
Link: https://lore.kernel.org/r/Z_kTqPX5Mjruq1pL@intel.com
</content>
</entry>
<entry>
<title>drm/xe/bmg: Add one additional PCI ID</title>
<updated>2025-04-07T20:16:06Z</updated>
<author>
<name>Matt Roper</name>
<email>matthew.d.roper@intel.com</email>
</author>
<published>2025-03-25T22:47:10Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=5529df92b8e8cbb4b14a226665888f74648260ad'/>
<id>urn:sha1:5529df92b8e8cbb4b14a226665888f74648260ad</id>
<content type='text'>
One additional BMG PCI ID has been added to the spec; make sure our
driver recognizes devices with this ID properly.

Bspec: 68090
Cc: stable@vger.kernel.org # v6.12+
Reviewed-by: Clint Taylor &lt;Clinton.A.Taylor@intel.com&gt;
Reviewed-by: Lucas De Marchi &lt;lucas.demarchi@intel.com&gt;
Link: https://lore.kernel.org/r/20250325224709.4073080-2-matthew.d.roper@intel.com
Signed-off-by: Matt Roper &lt;matthew.d.roper@intel.com&gt;
(cherry picked from commit cca9734ebe55f6af11ce8d57ca1afdc4d158c808)
Signed-off-by: Lucas De Marchi &lt;lucas.demarchi@intel.com&gt;
</content>
</entry>
<entry>
<title>agp/intel-gtt: Add intel_gmch_gtt_read_entry()</title>
<updated>2025-04-01T23:16:12Z</updated>
<author>
<name>Ville Syrjälä</name>
<email>ville.syrjala@linux.intel.com</email>
</author>
<published>2025-03-13T14:08:31Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=8f0d3618c6b31b1f8ff0c6c08cf6b101e56d6f8b'/>
<id>urn:sha1:8f0d3618c6b31b1f8ff0c6c08cf6b101e56d6f8b</id>
<content type='text'>
i915 wants to read out the PTE(s) populated by the BIOS/GOP
to verify that the framebuffer is in the correct location.
Introduce intel_gmch_gtt_read_entry() that reads out the
PTE and decodes it to a somewhat abstract form. For now
we just return the dma_addr, present bit, and local memory
bit. I didn't bother with the snoop bit/etc.

Signed-off-by: Ville Syrjälä &lt;ville.syrjala@linux.intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20250313140838.29742-4-ville.syrjala@linux.intel.com
Reviewed-by: Jouni Högander &lt;jouni.hogander@intel.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'drm-xe-next-2025-02-24' of https://gitlab.freedesktop.org/drm/xe/kernel into drm-next</title>
<updated>2025-02-27T00:08:29Z</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2025-02-27T00:08:22Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=33e26f3544a558e7476eb221ff33173759b3a116'/>
<id>urn:sha1:33e26f3544a558e7476eb221ff33173759b3a116</id>
<content type='text'>
UAPI Changes:
 - Add mmap support for PCI memory barrier (Tejas, Matthew Auld)
 - Enable integration with perf pmu, exposing event counters: for now, just
   GT C6 residency (Vinay, Lucas)
 - Add "survivability mode" to allow putting the driver in a state capable of
   firmware upgrade on critical failures (Riana, Rodrigo)
 - Add PXP HWDRM support and enable for compatible platforms:
   Meteor Lake and Lunar Lake (Daniele, John Harrison)
 - Expose package and vram temperature over hwmon subsystem (Raag, Badal, Rodrigo)

Cross-subsystem Changes:
 - Backmege drm-next to synchronize with i915 display and other internal APIs

Display Changes (including i915):
 - Device probe re-order to help with flicker-free boot (Maarten)
 - Align watermark, hpd and dsm with i915 (Rodrigo)
 - Better abstraction for d3cold (Rodrigo)

Driver Changes:
 - Make sure changes to ccs_mode is with helper for gt sync reset (Maciej)
 - Drop mmio_ext abstraction since it didn't prove useful in its current form
   (Matt Roper)
 - Reject BO eviction if BO is bound to current VM (Oak, Thomas Hellström)
 - Add GuC Power Conservation debugfs (Rodrigo)
 - L3 cache topology updates for Xe3 (Francois, Matt Atwood)
 - Better logging about missing GuC logs (John Harrison)
 - Better logging for hwconfig-related data availability (John Harrison)
 - Tracepoint updates for xe_bo_create, xe_vm and xe_vma (Oak)
 - Add missing SPDX licenses (Francois)
 - Xe suballocator imporovements (Michal Wajdeczko)
 - Improve logging for native vs SR-IOV driver mode (Satyanarayana)
 - Make sure VF bootstrap is not attempted in execlist mode (Maarten)
 - Add GuC Buffer Cache abstraction for some CTB H2G actions and use
   during VF provisioning (Michal Wajdeczko)
 - Better synchronization in gtidle for new users (Vinay)
 - New workarounds for Panther Lake (Nirmoy, Vinay)
 - PCI ID updates for Panther Lake (Matt Atwood)
 - Enable SR-IOV for Panther Lake (Michal Wajdeczko)
 - Update MAINTAINERS to stop directing xe changes to drm-misc (Lucas)
 - New PCI IDs for Battle Mage (Shekhar)
 - Better pagefault logging (Francois)
 - SR-IOV fixes and refactors for past and new platforms (Michal Wajdeczko)
 - Platform descriptor refactors and updates (Sai Teja)
 - Add gt stats debugfs (Francois)
 - Add guc_log debugfs to dump to dmesg (Lucas)
 - Abstract per-platform LMTT availability (Piotr Piórkowski)
 - Refactor VRAM manager location (Piotr Piórkowski)
 - Add missing xe_pm_runtime_put when forcing wedged mode (Shuicheng)
 - Fix possible lockup when forcing wedged mode (Xin Wang)
 - Probe refactors to use cleanup actions with better error handling (Lucas)
 - XE_IOCTL_DBG clarification for userspace (Maarten)
 - Better xe_mmio initialization and abstraction (Ilia)
 - Drop unnecessary GT lookup (Matt Roper)
 - Skip client engine usage from fdinfo for VFs (Marcin Bernatowicz)
 - Allow to test xe_sync_entry_parse with error injection (Priyanka)
 - OA fix for polled read (Umesh)

Signed-off-by: Dave Airlie &lt;airlied@redhat.com&gt;

From: Lucas De Marchi &lt;lucas.demarchi@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/m3gbuh32wgiep43i4zxbyhxqbenvtgvtao5sczivlasj7tikwv@dmlba4bfg2ny
</content>
</entry>
<entry>
<title>Merge drm/drm-next into drm-intel-next</title>
<updated>2025-02-05T17:12:37Z</updated>
<author>
<name>Jani Nikula</name>
<email>jani.nikula@intel.com</email>
</author>
<published>2025-02-05T17:12:37Z</published>
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<id>urn:sha1:ea9f8f2b21795a5d80418a655bcb212d5b89e08f</id>
<content type='text'>
Sync with v6.14-rc1.

Signed-off-by: Jani Nikula &lt;jani.nikula@intel.com&gt;
</content>
</entry>
<entry>
<title>Merge drm/drm-next into drm-xe-next</title>
<updated>2025-01-30T22:35:52Z</updated>
<author>
<name>Lucas De Marchi</name>
<email>lucas.demarchi@intel.com</email>
</author>
<published>2025-01-30T22:35:52Z</published>
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<id>urn:sha1:220ed690436e919a523bd8cd0ca803268025d4b6</id>
<content type='text'>
Backmerge drm-next to get the common APIs and refactors as well as
getting the display changes from i915 in xe so the probe order can be
improved.

Signed-off-by: Lucas De Marchi &lt;lucas.demarchi@intel.com&gt;
</content>
</entry>
</feed>
