user/sven/linux.git/include/drm, branch next/master

Merge branch 'char-misc-next' of https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc.git

2026-04-09T13:56:14Z

Merge branch 'for-linux-next' of https://gitlab.freedesktop.org/drm/i915/kernel.git

2026-04-09T13:24:37Z

Merge branch 'drm-next' of https://gitlab.freedesktop.org/agd5f/linux.git

2026-04-09T13:24:36Z

Merge drm/drm-next into drm-intel-next

2026-04-08T21:10:49Z

Backmerge to unblock a topic branch for i915 and xe. Signed-off-by: Jani Nikula

drm/i915/pci: move intel_pci_config.h under include/drm/intel

2026-04-08T09:29:59Z

Since the PCI registers are used from both i915 display and core, move intel_pci_config.h to include/drm/intel/pci_config.h. Drop the intel_ prefix from the name to reduce tautology. With this, we can drop the corresponding xe display compat header. v2: Rebase Reviewed-by: Ville Syrjälä Link: https://patch.msgid.link/5aac6c711c3f0a09fc52f322455a4a4b35f80a82.1775590536.git.jani.nikula@intel.com Signed-off-by: Jani Nikula

drm/i915/mchbar: move intel_mchbar_regs.h under include/drm/intel

2026-04-08T09:29:59Z

Since the mchbar registers are used from both i915 display and core, move intel_mchbar_regs.h to include/drm/intel/mchbar_regs.h. Drop the intel_ prefix from the name to reduce tautology. With this, we can drop the corresponding xe display compat header. v2: Rebase Reviewed-by: Ville Syrjälä Link: https://patch.msgid.link/6c951b2c05db74ea517d52a3912986f7eb886422.1775590536.git.jani.nikula@intel.com Signed-off-by: Jani Nikula

ttm/pool: port to list_lru. (v2)

2026-04-07T20:52:47Z

This is an initial port of the TTM pools for write combined and uncached pages to use the list_lru. This makes the pool's more NUMA aware and avoids needing separate NUMA pools (later commit enables this). Cc: Christian Koenig Cc: Johannes Weiner Cc: Dave Chinner Reviewed-by: Christian König Signed-off-by: Dave Airlie

drm/display: Add drm helper to check pr optimization support

2026-04-07T09:56:54Z

Add api to check panel replay optimization supported or not to drm-core DP tunneling framework which can be used by other driver as well. v2: Split generic drm changes from Intel specific changes. [Jouni] Reviewed-by: Jouni Högander Suggested-by: Imre Deak Signed-off-by: Animesh Manna Acked-by: Maarten Lankhorst Link: https://patch.msgid.link/20260330133620.3750559-2-animesh.manna@intel.com

mei: lb: add late binding version 2

2026-04-06T09:39:55Z

The second Late Binding version allows to send payload bigger than client MTU by splitting it to chunks and uses separate firmware client for transfer. The component interface is unchanged and driver doing all splitting. Only one Late Binding version is supported by firmware. When Late binding version 2 is supported, the new client is advertised by firmware and existing MKHI will have version 2. This helps driver to select the right mode of work. Reviewed-by: Andy Shevchenko Reviewed-by: Badal Nilawar Signed-off-by: Alexander Usyskin Link: https://patch.msgid.link/20260405112326.1535208-3-alexander.usyskin@intel.com Signed-off-by: Greg Kroah-Hartman

drm/edid: Parse AMD Vendor-Specific Data Block

2026-04-03T17:45:49Z

Parse the AMD VSDB v3 from CTA extension blocks and store the result in struct drm_amd_vsdb_info, a new field of drm_display_info. This includes replay mode, panel type, and luminance ranges. Signed-off-by: Chenyu Chen Reviewed-by: Mario Limonciello (AMD) Signed-off-by: Alex Deucher