user/sven/linux.git/include/dt-bindings/pinctrl, branch v4.20

Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

2018-10-29T22:05:20Z

Pull ARM SoC device tree updates from Arnd Bergmann: "There are close to 800 indivudal changesets in this branch again, which feels like a lot. There are particularly many changes for the NVIDIA Tegra platform this time, in fact more than it has seen in the two years since the v4.9 merge window. Aside from this, it's been fairly normal, with lots of changes going into Renesas R-CAR, NXP i.MX, Allwinner Sunxi, Samsung Exynos, and TI OMAP. Most of the changes are for adding new features into existing boards, for brevity I'm only mentioning completely new machines and SoCs here. For the first time I think we have (slightly) more new 64-bit hardware than 32-bit: Two boards get added for TI OMAP: Moxa UC-2101 is an industrial computer, see https://www.moxa.com/product/UC-2100.htm; GTA04A5 is a minor variation of the motherboards of the GTA04 phone, see https://shop.goldelico.com/wiki.php?page=GTA04A5 Clearfog is a nice little board for quad-core Marvell Armada 8040 network processor, see https://www.solid-run.com/marvell-armada-family/clearfog-gt-8k/ Two additional server boards come with the Aspeed baseboard management controllers: Stardragon4800 is an arm64 reference platform made by HXT (based on Qualcomm's server chips), and TiogaPass is an Open Compute mainboard with x86 CPUs. Both use the ARM11 based AST2500 chips in the BMC. NXP i.MX usually sees a lot of new boards each release. This time there we only add one minor variant: ConnectCore 6UL SBC Pro uses the same SoM design as the ConnectCore 6UL SBC Express added later. However, there is a new chip, the i.MX6ULZ, which is an even smaller variant of the i.MX6ULL, with features removed. There is also support for the reference board design, the i.MX6ULZ 14x14 EVK. A new Raspberry Pi variant gets added, this one is the CM3 compute module based on bcm2837, it was launched in early 2017 but only now added to the kernel, both as 32-bit and as 64-bit files, as we tend to do for Raspberry Pi. On the Allwinner side, everything is again about cheap development boards, usually of the "Fruit Pi" variety. The new ones this time are: - Orange Pi Zero Plus2: http://www.orangepi.org/OrangePiZeroPlus2/ - Orange Pi One Plus: http://www.orangepi.org/OrangePiOneplus/ - Pine64 LTS: https://www.pine64.org/?product=pine-a64-lts - Banana Pi M2+ H5: http://www.banana-pi.org/m2plus.html The last one of these is now a 64-bit version of the earlier Banana Pi M2+ H3, with the same board layout. Similarly, for Rockchips, get get another variant of the 32-bit Asus Tinker board, the model 'S' based on rk3288, and three now boards based on the popular RK3399 chip: - ROC-RK3399-PC: https://libre.computer/products/boards/roc-rk3399-pc/ - Rock960: https://www.96boards.org/product/rock960/ - RockPro64: https://www.pine64.org/?page_id=61454 These are all quite powerful boards with lots of RAM and I/O, and the RK3399 is the same chip used in several Chromebooks. Finally, we get support for the PX30 (aka rk3326) chip, which is based on the low-end 64-bit Cortex-A35 CPU core. So far, only the evaluation board is supported. One more Banana Pi is added with a Mediatek chip: Banana Pi R64 is based on the MT7622 WiFi router platform, and the first product I've seen with a 64-bit Mediatek chip in that market: http://www.banana-pi.org/r64.html For HiSilicon, we gain support for the Hi3670 SoC and HiKey 370 development board, which are similar to the Hi3660 and Hikey 360 respectively, but add support for an NPU. Amlogic gets initial support for the Meson-G12A chip (S905D2), another quad-core Cortex-A53 SoC, and its evaluation platform. On the 32-bit side, we gain support for an actual end-user product, the Endless Computers Endless Mini based on Meson8b (S805), see https://endlessos.com/computers/ Qualcomm adds support for their MSM8998 SoC and evaluation platform. This chip is commonly known as the Snapdragon 835, and is used in high-end phones as well as low-end laptops. For Renesas, a very bare support for the r8a774a1 (RZ/G2M) is added, but no boards for this one. However, we do add boards for the previously added r8a77965 (R-Car M3-N): the M3NULCB Kingfisher and the M3NULCB Starter Kit Pro. While we have lots of DT changes for NVIDIA to update the existing files, the only board that gets added is the Toradex Colibri T20 on Colibri Evaluation Board for the old Tegra2. Synaptics add support for their AS370 SoC, which is part of the (formerly Marvell) Berlin line of set-top-box chips used e.g. in the various Google Chromecast. Only the .dtsi gets added at this point, no actual machines" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (721 commits) ARM: dts: socfgpa: remove ethernet aliases from dtsi arm64: dts: stratix10: add ethernet aliases dt-bindings: mediatek: Add bindig for MT7623 IOMMU and SMI dt-bindings: mediatek: Add JPEG Decoder binding for MT7623 dt-bindings: iommu: mediatek: Add binding for MT7623 dt-bindings: clock: mediatek: add support for MT7623 ARM: dts: mvebu: armada-385-db-88f6820-amc: auto-detect nand ECC properites ARM: dts: da850-lego-ev3: slow down A/DC as much as possible ARM: dts: da850-evm: Enable tca6416 on baseboard arm64: dts: uniphier: Add USB2 PHY nodes arm64: dts: uniphier: Add USB3 controller nodes ARM: dts: uniphier: Add USB2 PHY nodes ARM: dts: uniphier: Add USB3 controller nodes arm64: dts: meson-axg: s400: disable emmc arm64: dts: meson-axg: s400: add missing emmc pwrseq arm64: dts: clearfog-gt-8k: add PCIe slot description ARM: dts: at91: sama5d4_xplained: even nand memory partitions ARM: dts: at91: sama5d3_xplained: even nand memory partitions ARM: dts: at91: at91sam9x5cm: even nand memory partitions ARM: dts: at91: sama5d2_ptc_ek: fix bootloader env offsets ...

dt-bindings: pinctrl: renesas,rzn1-pinctrl: documentation

2018-10-02T10:16:39Z

The Renesas RZ/N1 device family PINCTRL node description. Based on a patch originally written by Michel Pollet at Renesas. Signed-off-by: Phil Edworthy Reviewed-by: Jacopo Mondi Signed-off-by: Geert Uytterhoeven

dt-bindings: Add Tegra PMC pad configuration bindings

2018-08-27T10:21:43Z

Document the PMC pinctrl bindings for pad power state and signaling voltage configuration. Both nvidia,tegra186-pmc.txt and nvidia,tegra20-pmc.txt are modified as they both cover SoC generations for which these bindings apply. Add a header defining Tegra PMC pad voltage configurations. Signed-off-by: Aapo Vienamo Acked-by: Jon Hunter Reviewed-by: Rob Herring Signed-off-by: Thierry Reding

Merge tag 'samsung-pinctrl-4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel

2018-07-25T20:47:03Z

Samsung pinctrl drivers changes for v4.19 1. Add handling of external wakeup interrupts mask inside the pin controller driver. Existing solution is spread between the driver and machine code. The machine code writes the mask but its value is taken from pin controller driver. This moves everything into pin controller driver allowing later to remove the cross-subsystem interaction. Also this is a necessary step for implementing later Suspend to RAM on ARMv8 Exynos5433. 2. Bring necessary suspend/resume callbacks for Exynos542x and Exynos5260. 3. Document hidden requirement about one external wakeup interrupts device node. 4. Minor documentation cleanups.

dt-bindings: pinctrl: samsung: Add SPDX license identifier

2018-07-24T19:59:17Z

Replace GPL license statement with SPDX license identifier (GPL-2.0). Signed-off-by: Krzysztof Kozlowski

pinctrl: at91-pio4: add support for drive strength

2018-07-16T12:46:11Z

Add support for the drive strength configuration. Usually, this value is expressed in mA. Since the numeric value depends on VDDIOP voltage, a value we can't retrieve at runtime, the controller uses low, medium and high to define the drive strength. The PIO controller accepts two values for the low drive configuration: 0 and 1. Most of the time, we don't care about the drive strength. So we keep the default value which is 0. The drive strength is advertised through the sysfs only when it has been explicitly set in the device tree i.e. if its value is different from 0. Signed-off-by: Ludovic Desroches Acked-by: Rob Herring Signed-off-by: Linus Walleij

pinctrl: mediatek: update pinmux defintions for MT7623

2018-05-02T12:36:08Z

Fulfill the pinmux macros for MT7623 Signed-off-by: Ryder Lee Reviewed-by: Rob Herring Signed-off-by: Linus Walleij

dt-bindings: pinctrl: mediatek: add bindings for I2C2 and SPI2 on MT7623

2018-03-02T07:44:24Z

Add missing pinctrl binding about I2C2 and SPI2 which would be used in devicetree related files. Signed-off-by: Sean Wang Cc: Rob Herring Cc: Mark Rutland Cc: Linus Walleij Cc: linux-gpio@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij

Merge tag 'pinctrl-v4.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2018-02-02T22:22:53Z

Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v4.16 kernel cycle. Like with GPIO it is actually a bit calm this time. Core changes: - After lengthy discussions and partly due to my ignorance, we have merged a patch making pinctrl_force_default() and pinctrl_force_sleep() reprogram the states into the hardware of any hogged pins, even if they are already in the desired state. This only apply to hogged pins since groups of pins owned by drivers need to be managed by each driver, lest they could not do things like runtime PM and put pins to sleeping state even if the system as a whole is not in sleep. New drivers: - New driver for the Microsemi Ocelot SoC. This is used in ethernet switches. - The X-Powers AXP209 GPIO driver was extended to also deal with pin control and moved over from the GPIO subsystem. This circuit is a mixed-mode integrated circuit which is part of AllWinner designs. - New subdriver for the Qualcomm MSM8998 SoC, core of a high end mobile devices (phones) chipset. - New subdriver for the ST Microelectronics STM32MP157 MPU and STM32F769 MCU from the STM32 family. - New subdriver for the MediaTek MT7622 SoC. This is used for routers, repeater, gateways and such network infrastructure. - New subdriver for the NXP (former Freescale) i.MX 6ULL. This SoC has multimedia features and target "smart devices", I guess in-car entertainment, in-flight entertainment, industrial control panels etc. General improvements: - Incremental improvements on the SH-PFC subdrivers for things like the CAN bus. - Enable the glitch filter on Baytrail GPIOs used for interrupts. - Proper handling of pins to GPIO ranges on the Semtec SX150X - An IRQ setup ordering fix on MCP23S08. - A good set of janitorial coding style fixes" * tag 'pinctrl-v4.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (102 commits) pinctrl: mcp23s08: fix irq setup order pinctrl: Forward declare struct device pinctrl: sunxi: Use of_clk_get_parent_count() instead of open coding pinctrl: stm32: add STM32F769 MCU support pinctrl: sx150x: Add a static gpio/pinctrl pin range mapping pinctrl: sx150x: Register pinctrl before adding the gpiochip pinctrl: sx150x: Unregister the pinctrl on release pinctrl: ingenic: Remove redundant dev_err call in ingenic_pinctrl_probe() pinctrl: sprd: Use seq_putc() in sprd_pinconf_group_dbg_show() pinctrl: pinmux: Use seq_putc() in pinmux_pins_show() pinctrl: abx500: Use seq_putc() in abx500_gpio_dbg_show() pinctrl: mediatek: mt7622: align error handling of mtk_hw_get_value call pinctrl: mediatek: mt7622: fix potential uninitialized value being returned pinctrl: uniphier: refactor drive strength get/set functions pinctrl: imx7ulp: constify struct imx_cfg_params_decode pinctrl: imx: constify struct imx_pinctrl_soc_info pinctrl: imx7d: simplify imx7d_pinctrl_probe pinctrl: imx: use struct imx_pinctrl_soc_info as a const pinctrl: sunxi-pinctrl: fix pin funtion can not be match correctly. pinctrl: qcom: Add msm8998 pinctrl driver ...

ARM: dts: am43xx: Fix inverted DS0_PULL_UP_DOWN_EN macro

2017-12-15T16:44:00Z

Due to a mistake in documentation the DS0_PULL_UP_DOWN_EN macro was mistakenly defined as an active high bit, however setting the bit actually disables the internal pull resistor on the pin, so correct this macro and introduce a new DS0_PULL_UP_DOWN_DIS macro with the proper bit value set now that the documentation has been updated. Change based on AM437x Techninal Reference Manual SPRUHL7G Revised June 2017 Section 7.2.1. Signed-off-by: Dave Gerlach Signed-off-by: Tony Lindgren