user/sven/linux.git/include/linux/brcmphy.h, branch v3.18.61

net: phy: add BCM7425 and BCM7429 PHYs

2014-10-02T02:12:48Z

Signed-off-by: Petri Gynther Acked-by: Florian Fainelli Signed-off-by: David S. Miller

net: bcmgenet: remove PHY_BRCM_100MBPS_WAR

2014-09-19T20:27:07Z

Now that we have removed the need for the PHY_BRCM_100MBPS_WAR flag, we can remove it from the GENET driver and the broadcom shared header file. The PHY driver checks the PHY supported bitmask instead. Signed-off-by: Florian Fainelli Signed-off-by: David S. Miller

net: phy: broadcom: add helper for PHY revision and patch level

2014-09-19T20:27:07Z

The Broadcom BCM7xxx internal PHYs do not contain any useful revision information in the low 4-bits of their MII_PHYSID2 (MII register 3) which could allow us to properly identify them. As a result, we need the actual hardware block integrating these PHYs: GENET or the SF2 switch to tell us what revision they are built with. To assist with that, add two helper macros for fetching the the PHY revision and patch level from the struct phy_device::dev_flags. Signed-off-by: Florian Fainelli Signed-off-by: David S. Miller

net: phy: bcm7xxx: add BCM7250 and BCM7364 PHY entries

2014-08-28T06:16:13Z

Add two new entries to the Broadcom BCM7xxx internal PHY driver for BCM7250 and BCM7364 chips. Those chips share the usual 28nm process Gigabit PHY sequence and require the same workarounds so far. Signed-off-by: Florian Fainelli Signed-off-by: David S. Miller

net: phy: broadcom: add new Broadcom OUI

2014-08-28T06:16:13Z

Broadcom started to use a new OUI for its 2013 and newer products: D4-01-29 which translates into 0xae025000 for a 32-bits OUI, add its definition. Signed-off-by: Florian Fainelli Signed-off-by: David S. Miller

net: phy: broadcom: fix PHY_BCM_OUI_4

2014-08-28T06:16:12Z

PHY_BCM_OUI_4 is missing two significant digits that actually make it an OUI, add those missing bits so it becomes usable again for matching. Fixes: b560a58c45c6 ("net: phy: add Broadcom BCM7xxx internal PHY driver") Signed-off-by: Florian Fainelli Signed-off-by: David S. Miller

net: phy: bcm7xxx: enable EEE at the PHY level

2014-08-23T18:39:09Z

The 28nm Gigabit PHY on BCM7xxx chips comes out of reset with absolutely no EEE capabilities, such that we would actually return that we do not support EEE when accessing 3.20 (MDIO_PCS_EEE_ABLE) registers. Poke through the vendor-specific C45 register to enable EEE globally at the PHY level, and advertise supported EEE modes. Signed-off-by: Florian Fainelli Signed-off-by: David S. Miller

net: phy: broadcom: move shadow 0x1C register accessors to brcmphy.h

2014-08-23T18:38:53Z

The shadow register 0x1C is used both by the BCM54xxx PHYs and the BCM7xxx internal PHYs, move the accessors to a common location so both drivers can use them. Signed-off-by: Florian Fainelli Signed-off-by: David S. Miller

net: phy: broadcom: extract all registers to brcmphy.h

2014-08-23T18:38:53Z

Commit 439d39a9ac8fbbba9c04581361188f33f21ced50 ("net: phy: broadcom: extract register definitions") added a bunch of registers to brcmphy.h but left some to broadcom.c, move all of them to the header file since the BCM54xx and BCM7xxx PHY drivers do share all of these registers. Signed-off-by: Florian Fainelli Signed-off-by: David S. Miller

net: phy: bcm7xxx: remove 28nm wildcard entry

2014-08-17T02:13:33Z

A wildcard entry with the 32-bits OUI 0x600d8400 was added as part of the BCM7xxx internal PHY driver, but that entry might match other PHYs that are not covered by this driver, so let's just remove it. Fixes: b560a58c45c6 ("net: phy: add Broadcom BCM7xxx internal PHY driver") Signed-off-by: Florian Fainelli Signed-off-by: David S. Miller