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<title>user/sven/linux.git/include/linux/clk/tegra.h, branch v4.19.135</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v4.19.135</id>
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<updated>2018-03-08T18:18:08Z</updated>
<entry>
<title>clk: tegra: MBIST work around for Tegra210</title>
<updated>2018-03-08T18:18:08Z</updated>
<author>
<name>Peter De Schrijver</name>
<email>pdeschrijver@nvidia.com</email>
</author>
<published>2018-01-25T14:00:12Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=e403d00573431e1e3de1710a91c6090c60ec16af'/>
<id>urn:sha1:e403d00573431e1e3de1710a91c6090c60ec16af</id>
<content type='text'>
Tegra210 has a hw bug which can cause IP blocks to lock up when ungating a
domain. The reason is that the logic responsible for resetting the memory
built-in self test mode can come up in an undefined state because its
clock is gated by a second level clock gate (SLCG). Work around this by
making sure the logic will get some clock edges by ensuring the relevant
clock is enabled and temporarily override the relevant SLCGs.
Unfortunately for some IP blocks, the control bits for overriding the
SLCGs are not in CAR, but in the IP block itself. This means we need to
map a few extra register banks in the clock code.

Signed-off-by: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Reviewed-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Tested-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Tested-by: Hector Martin &lt;marcan@marcan.st&gt;
Tested-by: Andre Heider &lt;a.heider@gmail.com&gt;
Tested-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;

fixup mbist
</content>
</entry>
<entry>
<title>clk: tegra: Add SATA seq input control</title>
<updated>2017-03-20T13:26:03Z</updated>
<author>
<name>Peter De Schrijver</name>
<email>pdeschrijver@nvidia.com</email>
</author>
<published>2017-03-15T15:42:05Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=59af78d78db8bde6a63e09772aa44192f772fa96'/>
<id>urn:sha1:59af78d78db8bde6a63e09772aa44192f772fa96</id>
<content type='text'>
This will be used by the powergating driver to ensure proper sequencer
state when the SATA domain is powergated.

Signed-off-by: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>clk: tegra: Handle UTMIPLL IDDQ</title>
<updated>2017-03-20T13:09:05Z</updated>
<author>
<name>Peter De Schrijver</name>
<email>pdeschrijver@nvidia.com</email>
</author>
<published>2017-02-28T15:19:24Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=3843832fc8cadc2d48ba4ea4cd350a696906ac42'/>
<id>urn:sha1:3843832fc8cadc2d48ba4ea4cd350a696906ac42</id>
<content type='text'>
Export UTMIPLL IDDQ functions. These will be needed when powergating the
XUSB partition.

Signed-off-by: BH Hsieh &lt;bhsieh@nvidia.com&gt;
Signed-off-by: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs</title>
<updated>2016-04-28T10:41:44Z</updated>
<author>
<name>Andrew Bresticker</name>
<email>abrestic@chromium.org</email>
</author>
<published>2015-06-18T21:28:40Z</published>
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<id>urn:sha1:3358d2d9f47af86bdd71edb24b361f72a54ec04e</id>
<content type='text'>
On Tegra210, hardware control of the SATA and XUSB pad PLLs must be
done during the UPHY enable sequence rather than the PLLE enable
sequence.  Export functions to do this so that hardware control can
be enabled from the XUSB padctl driver.

Signed-off-by: Andrew Bresticker &lt;abrestic@chromium.org&gt;
Signed-off-by: Rhyland Klein &lt;rklein@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>clk: tegra: Properly include clk.h</title>
<updated>2015-07-20T18:11:17Z</updated>
<author>
<name>Stephen Boyd</name>
<email>sboyd@codeaurora.org</email>
</author>
<published>2015-06-19T22:00:46Z</published>
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<id>urn:sha1:584ac4e935a1f905d67c8fa3fbe8e32d384721f1</id>
<content type='text'>
Clock provider drivers generally shouldn't include clk.h because
it's the consumer API. Only include clk.h in files that are using
it. Also add in a clkdev.h include that was missing in a file
using clkdev APIs.

Cc: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Cc: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: tegra: make tegra_clocks_apply_init_table() arch_initcall</title>
<updated>2015-02-02T13:47:28Z</updated>
<author>
<name>Peter De Schrijver</name>
<email>pdeschrijver@nvidia.com</email>
</author>
<published>2014-12-16T20:38:27Z</published>
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<id>urn:sha1:d0a57bd5b53d6b7fe7a6c626023737436b5df630</id>
<content type='text'>
tegra_clocks_apply_init_table() needs to be called after the udelay
loop has been calibrated (see commit
441f199a37cfd66c5dd8dd45490bd3ea6971117d ("clk: tegra: defer
application of init table") for why that is).  On existing Tegra SoCs
this was done by calling tegra_clocks_apply_init_table() from
tegra_dt_init(). To make this also work on ARM64, we need to change
this into an initcall. tegra_dt_init() is called from
customize_machine which is an arch_initcall. Therefore this should
also work on existing 32bit Tegra SoCs.

Tested on Tegra20 (ventana), Tegra30 (beaverboard), Tegra124 (jetson TK1) and
Tegra132.

Signed-off-by: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
[paul@pwsan.com: tweaked the commit message]
Signed-off-by: Paul Walmsley &lt;paul@pwsan.com&gt;
Signed-off-by: Paul Walmsley &lt;pwalmsley@nvidia.com&gt;
Cc: Thierry Reding &lt;treding@nvidia.com&gt;
Cc: Prashant Gaikwad &lt;pgaikwad@nvidia.com&gt;
Cc: Mike Turquette &lt;mturquette@linaro.org&gt;
Cc: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
Cc: Stephen Warren &lt;swarren@wwwdotorg.org&gt;
Cc: Thierry Reding &lt;thierry.reding@gmail.com&gt;
Cc: Alexandre Courbot &lt;gnurou@gmail.com&gt;
</content>
</entry>
<entry>
<title>clk: tegra: remove legacy reset APIs</title>
<updated>2013-12-11T23:45:07Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2013-11-06T23:58:16Z</published>
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<id>urn:sha1:2ae77527bb1a510070d039aaa22d1ae9a5807b6f</id>
<content type='text'>
Now that no code uses the custom Tegra module reset API, we can remove
its implementation.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Reviewed-by: Thierry Reding &lt;treding@nvidia.com&gt;
Acked-By: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
</content>
</entry>
<entry>
<title>clk: tegra: fix ifdef for tegra_periph_reset_assert inline</title>
<updated>2013-06-24T21:17:59Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2013-06-24T19:05:56Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=45e3ec3784aec0d194740b75b547bfabca448ff3'/>
<id>urn:sha1:45e3ec3784aec0d194740b75b547bfabca448ff3</id>
<content type='text'>
Commit 7064f6b "clk: tegra: provide tegra_periph_reset_assert
alternative" added ifdef'd static inline versions of some functions,
but tested ARCH_TEGRA rather than CONFIG_ARCH_TEGRA, thus disabling
these function in all cases. In some cases, this caused HW modules to
misbehave; for example, the Tegra I2C driver BUG()d during boot on
Seaboard.

Reported-by: Olof Johansson &lt;olof@lixom.net&gt;
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Tested-by: Paul Walmsley &lt;pwalmsley@nvidia.com&gt;
Signed-off-by: Mike Turquette &lt;mturquette@linaro.org&gt;
</content>
</entry>
<entry>
<title>clk: tegra: provide tegra_periph_reset_assert alternative</title>
<updated>2013-06-22T18:03:09Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2013-06-21T20:32:26Z</published>
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<id>urn:sha1:7064f6bd86278029348c36d30bd325e7e05b6fee</id>
<content type='text'>
We have some tegra device drivers that are written to be platform
independent but still use the tegra specific tegra_periph_reset_assert
function. In order to build and link them without errors,
this provides a static inline version of these functions that
does nothing when Tegra support is disabled.

Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Acked-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Mike Turquette &lt;mturquette@linaro.org&gt;
[mturquette@linaro.org: fixed up trivial merge issue]
</content>
</entry>
<entry>
<title>clk: tegra: Use common of_clk_init function</title>
<updated>2013-05-31T19:57:25Z</updated>
<author>
<name>Prashant Gaikwad</name>
<email>pgaikwad@nvidia.com</email>
</author>
<published>2013-05-27T07:40:09Z</published>
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<id>urn:sha1:061cec925f212f145516e826f39962624a738ded</id>
<content type='text'>
Use common of_clk_init() function for clocks initialization.

Signed-off-by: Prashant Gaikwad &lt;pgaikwad@nvidia.com&gt;
Reviewed-by: Thierry Reding &lt;thierry.reding@gmail.com&gt;
Acked-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Mike Turquette &lt;mturquette@linaro.org&gt;
</content>
</entry>
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