user/sven/linux.git/include/linux/clk, branch v4.20.13

Merge branch 'clk-ti' into clk-next

2018-10-18T22:41:21Z

* clk-ti: clk: ti: Prepare for remove of OF node name clk: Clean up suspend/resume coding style clk: ti: Add functions to save/restore clk context clk: clk: Add clk_gate_restore_context function clk: Add functions to save/restore clock context en-masse clk: ti: dra7: add new clkctrl data clk: ti: dra7xx: rename existing clkctrl data as compat data clk: ti: am43xx: add new clkctrl data for am43xx clk: ti: am43xx: rename existing clkctrl data as compat data clk: ti: am33xx: add new clkctrl data for am33xx clk: ti: am33xx: rename existing clkctrl data as compat data clk: ti: clkctrl: replace dashes from clkdm name with underscore clk: ti: clkctrl: support multiple clkctrl nodes under a cm node dt-bindings: clock: dra7xx: add clkctrl indices for new data layout dt-bindings: clock: am43xx: add clkctrl indices for new data layout dt-bindings: clock: am33xx: add clkctrl indices for new data layout

clk: ti: Add functions to save/restore clk context

2018-10-03T12:29:19Z

SoCs like AM43XX lose clock registers context during RTC-only suspend. Hence add functions to save/restore the clock registers context. Signed-off-by: Keerthy Signed-off-by: Russ Dill Acked-by: Tony Lindgren Signed-off-by: Tero Kristo

clk: ti: clkctrl: support multiple clkctrl nodes under a cm node

2018-10-03T12:02:26Z

Currently, only one clkctrl node can be added under a specific CM node due to limitation with the implementation. Modify the code to pick-up clockdomain name from the clkctrl node instead of CM node if provided. Also, add a new flag to the TI clock driver so that both modes can be supported simultaneously. Signed-off-by: Tero Kristo Tested-by: Tony Lindgren

clk: renesas: Convert to SPDX identifiers

2018-09-29T00:16:37Z

This patch updates license to use SPDX-License-Identifier instead of verbose license text. Signed-off-by: Kuninori Morimoto [rebased against clk-spdx] Signed-off-by: Geert Uytterhoeven Reviewed-by: Simon Horman Signed-off-by: Stephen Boyd

ARM: at91: pm: add PMC fast startup registers defines

2018-07-17T13:08:07Z

Add PMC fast startup registers defines. Signed-off-by: Claudiu Beznea Signed-off-by: Alexandre Belloni

ARM: at91: pm: Add ULP1 mode support

2018-07-17T13:08:02Z

In the ULP1 mode, in order to achieve the lowest power consumption with the system in retention mode and be able to resume on the wake up events, all the clocks are shut off, inclusive the embedded 12MHz RC oscillator, and the number of wake up sources is limited as well. When the wake up event is asserted, the embedded 12MHz RC oscillator restarts automatically. The ULP1 (Ultra Low-power mode 1) is introduced by SAMA5D2. The previous size of pm_suspend.o was 2148 bytes. With the addition of ULP1 mode the new size of pm_suspend.o raised at 2456 bytes. Signed-off-by: Wenyou Yang Signed-off-by: Ludovic Desroches [claudiu.beznea@microchip.com: aligned with 4.18-rc1] Signed-off-by: Claudiu Beznea Signed-off-by: Alexandre Belloni

clk: davinci: Fix link errors when not all SoCs are enabled

2018-05-30T19:48:49Z

This fixes linker errors due to undefined symbols when one or more of the TI DaVinci SoCs is not enabled in the kernel config. Signed-off-by: David Lechner Signed-off-by: Michael Turquette Link: lkml.kernel.org/r/20180525181150.17873-10-david@lechnology.com

clk: davinci: psc: allow for dev == NULL

2018-05-30T19:48:44Z

On some davinci SoCs, we need to register the PSC clocks during early boot because they are needed for clocksource/clockevent. These changes allow for dev == NULL because in this case, we won't have a platform device for the clocks. Signed-off-by: David Lechner Reviewed-by: Sekhar Nori Signed-off-by: Michael Turquette Link: lkml.kernel.org/r/20180525181150.17873-9-david@lechnology.com

clk: davinci: pll: allow dev == NULL

2018-05-30T19:48:35Z

This modifies the TI Davinci PLL clock driver to allow for the case when dev == NULL. On some (most) SoCs that use this driver, the PLL clock needs to be registered during early boot because it is used for clocksource/clkevent and there will be no platform device available. Signed-off-by: David Lechner Reviewed-by: Sekhar Nori Signed-off-by: Michael Turquette Link: lkml.kernel.org/r/20180525181150.17873-7-david@lechnology.com

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

2018-04-13T22:51:06Z

Pull clk updates from Stephen Boyd: "The large diff this time around is from the addition of a new clk driver for the TI Davinci family of SoCs. So far those clks have been supported with a custom implementation of the clk API in the arch port instead of in the CCF. With this driver merged we're one step closer to having a single clk API implementation. The other large diff is from the Amlogic clk driver that underwent some major surgery to use regmap. Beyond that, the biggest hitter is Samsung which needed some reworks to properly handle clk provider power domains and a bunch of PLL rate updates. The core framework was fairly quiet this round, just getting some cleanups and small fixes for some of the more esoteric features. And the usual set of driver non-critical fixes, cleanups, and minor additions are here as well. Core: - Rejig clk_ops::init() to be a little earlier for phase/accuracy ops - debugfs ops macroized to shave some lines of boilerplate code - Always calculate the phase instead of caching it in clk_get_phase() - More __must_check on bulk clk APIs New Drivers: - TI's Davinci family of SoCs - Intel's Stratix10 SoC - stm32mp157 SoC - Allwinner H6 CCU - Silicon Labs SI544 clock generator chip - Renesas R-Car M3-N and V3H SoCs - i.MX6SLL SoCs Removed Drivers: - ST-Ericsson AB8540/9540 Updates: - Mediatek MT2701 and MT7622 audsys support and MT2712 updates - STM32F469 DSI and STM32F769 sdmmc2 support - GPIO clks can sleep now - Spreadtrum SC9860 RTC clks - Nvidia Tegra MBIST workarounds and various minor fixes - Rockchip phase handling fixes and a memory leak plugged - Renesas drivers switch to readl/writel from clk_readl/clk_writel - Renesas gained CPU (Z/Z2) and watchdog support - Rockchip rk3328 display clks and rk3399 1.6GHz PLL support - Qualcomm PM8921 PMIC XO buffers - Amlogic migrates to regmap APIs - TI Keystone clk latching support - Allwinner H3 and H5 video clk fixes - Broadcom BCM2835 PLLs needed another bit to enable - i.MX6SX CKO mux fix and i.MX7D Video PLL divider fix - i.MX6UL/ULL epdc_podf support - Hi3798CV200 COMBPHY0 and USB2_OTG_UTMI and phase support for eMMC" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (233 commits) clk: davinci: add a reset lookup table for psc0 clk: imx: add clock driver for imx6sll dt-bindings: imx: update clock doc for imx6sll clk: imx: add new gate/gate2 wrapper funtion clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux clk: cs2000: set pm_ops in hibernate-compatible way clk: bcm2835: De-assert/assert PLL reset signal when appropriate clk: imx7d: Move clks_init_on before any clock operations clk: imx7d: Correct ahb clk parent select clk: imx7d: Correct dram pll type clk: imx7d: Add USB clock information clk: socfpga: stratix10: add clock driver for Stratix10 platform dt-bindings: documentation: add clock bindings information for Stratix10 clk: ti: fix flag space conflict with clkctrl clocks clk: uniphier: add additional ethernet clock lines for Pro4 clk: uniphier: add SATA clock control support clk: uniphier: add PCIe clock control support clk: Add driver for the si544 clock generator chip clk: davinci: Remove redundant dev_err calls clk: uniphier: add ethernet clock control support for PXs3 ...