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<title>user/sven/linux.git/include/linux/firmware, branch v6.13.7</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v6.13.7</id>
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<updated>2024-11-26T01:24:51Z</updated>
<entry>
<title>Merge tag 'pinctrl-v6.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl</title>
<updated>2024-11-26T01:24:51Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2024-11-26T01:24:51Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=2d32fba02e0e5b67fb3a4ea51dde80c0db83f1c1'/>
<id>urn:sha1:2d32fba02e0e5b67fb3a4ea51dde80c0db83f1c1</id>
<content type='text'>
Pull pin control updates from Linus Walleij:
 "No core changes this time.

  New drivers:

   - Xlinix Versal pin control driver

   - Ocelot LAN969x pin control driver

   - T-Head TH1520 RISC-V SoC pin control driver

   - Qualcomm SM8750, IPQ5424, QCS8300, SAR2130P and QCS615 SoC pin
     control drivers

   - Qualcomm SM8750 LPASS (low power audio subsystem) pin control
     driver

   - Qualcomm PM8937 mixsig IC pin control support, GPIO and MPP
     (multi-purpose-pin)

   - Samsung Exynos8895 and Exynos9810 SoC pin control driver

   - SpacemiT K1 SoC pin control driver

   - Airhoa EN7581 IC pin control driver

  Improvements:

   - The Renesas subdriver now supports schmitt-trigger and open drain
     pin configurations if the hardware supports it

   - Support GPIOF and GPIOG banks in the Aspeed G6 SoC

   - Support the DSW community in the Intel Elkhartlake SoC"

* tag 'pinctrl-v6.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (105 commits)
  pinctrl: airoha: Use unsigned long for bit search
  pinctrl: k210: Undef K210_PC_DEFAULT
  pinctrl: qcom: spmi: fix debugfs drive strength
  pinctrl: qcom: Add sm8750 pinctrl driver
  dt-bindings: pinctrl: qcom: Add sm8750 pinctrl
  pinctrl: cy8c95x0: remove unneeded goto labels
  pinctrl: cy8c95x0: embed iterator to the for-loop
  pinctrl: cy8c95x0: Use temporary variable for struct device
  pinctrl: cy8c95x0: use flexible sleeping in reset function
  pinctrl: cy8c95x0: switch to using devm_regulator_get_enable()
  pinctrl: cy8c95x0: Use 2-argument strscpy()
  dt-bindings: pinctrl: sx150xq: allow gpio line naming
  pinctrl: single: add marvell,pxa1908-padconf compatible
  dt-bindings: pinctrl: pinctrl-single: add marvell,pxa1908-padconf compatible
  dt-bindings: pinctrl: correct typo of description for cv1800
  pinctrl: qcom: spmi-mpp: Add PM8937 compatible
  dt-bindings: pinctrl: qcom,pmic-mpp: Document PM8937 compatible
  pinctrl: qcom-pmic-gpio: add support for PM8937
  dt-bindings: pinctrl: qcom,pmic-gpio: add PM8937
  pinctrl: Use of_property_present() for non-boolean properties
  ...
</content>
</entry>
<entry>
<title>Merge tag 'qcom-drivers-for-6.13-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers</title>
<updated>2024-11-13T17:38:56Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2024-11-13T17:38:51Z</published>
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<id>urn:sha1:1876c788bba174660b538dcf5d1bc2b75d7f6d66</id>
<content type='text'>
A few more Qualcomm driver updates for v6.13

Make the Adreno driver invoke the SMMU aperture setup firmware function,
which is required to allow the GPU to manage per-process page tables in
some firmware versions - as an example Rb3Gen2 has no GPU without this.

Add X1E Devkit to the list of devices that has functional EFI variable
access through the uefisecapp.

Flip the "manual slice configuration quirk" in the Qualcomm LLCC driver,
as this only applies to a single platform, and introduce support for
QCS8300, QCS615, SAR2130P, and SAR1130P.

Lastly, add IPQ5424 and IPQ5404 to the Qualcomm socinfo driver.

* tag 'qcom-drivers-for-6.13-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
  soc: qcom: ice: Remove the device_link field in qcom_ice
  drm/msm/adreno: Setup SMMU aparture for per-process page table
  firmware: qcom: scm: Introduce CP_SMMU_APERTURE_ID
  soc: qcom: socinfo: add IPQ5424/IPQ5404 SoC ID
  dt-bindings: arm: qcom,ids: add SoC ID for IPQ5424/IPQ5404
  soc: qcom: llcc: Flip the manual slice configuration condition
  dt-bindings: firmware: qcom,scm: Document sm8750 SCM
  firmware: qcom: uefisecapp: Allow X1E Devkit devices
  soc: qcom: llcc: Add LLCC configuration for the QCS8300 platform
  dt-bindings: cache: qcom,llcc: Document the QCS8300 LLCC
  soc: qcom: llcc: Add configuration data for QCS615
  dt-bindings: cache: qcom,llcc: Document the QCS615 LLCC
  soc: qcom: llcc: add support for SAR2130P and SAR1130P
  soc: qcom: llcc: use deciman integers for bit shift values
  dt-bindings: cache: qcom,llcc: document SAR2130P and SAR1130P

Link: https://lore.kernel.org/r/20241113032425.356306-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>firmware: qcom: scm: Introduce CP_SMMU_APERTURE_ID</title>
<updated>2024-11-11T18:03:26Z</updated>
<author>
<name>Bjorn Andersson</name>
<email>bjorn.andersson@oss.qualcomm.com</email>
</author>
<published>2024-11-10T17:33:40Z</published>
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<id>urn:sha1:1af75b2ad08bd5977c51c2d0fc11741a4c0a48d9</id>
<content type='text'>
The QCOM_SCM_SVC_MP service provides QCOM_SCM_MP_CP_SMMU_APERTURE_ID,
which is used to trigger the mapping of register banks into the SMMU
context for per-processes page tables to function (in case this isn't
statically setup by firmware).

This is necessary on e.g. QCS6490 Rb3Gen2, in order to avoid "CP | AHB
bus error"-errors from the GPU.

Introduce a function to allow the msm driver to invoke this call.

Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@oss.qualcomm.com&gt;
Reviewed-by: Rob Clark &lt;robdclark@gmail.com&gt;
Link: https://lore.kernel.org/r/20241110-adreno-smmu-aparture-v2-1-9b1fb2ee41d4@oss.qualcomm.com
Signed-off-by: Bjorn Andersson &lt;andersson@kernel.org&gt;
</content>
</entry>
<entry>
<title>firmware: xilinx: add support for new SMC call format</title>
<updated>2024-10-02T10:54:45Z</updated>
<author>
<name>Ronak Jain</name>
<email>ronak.jain@amd.com</email>
</author>
<published>2024-09-20T05:55:01Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=92fb71333d5737d0296fb968a653dfda4b225175'/>
<id>urn:sha1:92fb71333d5737d0296fb968a653dfda4b225175</id>
<content type='text'>
Added zynqmp_pm_invoke_fw_fn() to use new SMC format in which
lower 12 bits of SMC id are fixed and firmware header is moved to
subsequent SMC arguments. The new SMC format supports full request and
response buffers.

Added zynqmp_pm_get_sip_svc_version() to get SiP SVC version
number to check if TF-A is newer or older and use the SMC format
accordingly to handle backward compatibility.

Used new SMC format for PM_QUERY_DATA API as more response values are
required in it.

Signed-off-by: Ronak Jain &lt;ronak.jain@amd.com&gt;
Signed-off-by: Jay Buddhabhatti &lt;jay.buddhabhatti@amd.com&gt;
Link: https://lore.kernel.org/r/20240920055501.2658642-1-ronak.jain@amd.com
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</content>
</entry>
<entry>
<title>firmware: xilinx: use u32 for reset ID in reset APIs</title>
<updated>2024-10-02T07:15:30Z</updated>
<author>
<name>Ronak Jain</name>
<email>ronak.jain@amd.com</email>
</author>
<published>2024-08-30T10:00:42Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=f33d6099edf78e3c97900c0173fedbfecc025a9e'/>
<id>urn:sha1:f33d6099edf78e3c97900c0173fedbfecc025a9e</id>
<content type='text'>
Refactors the reset handling mechanisms by replacing the reset ID's
enum type with a u32. This update improves flexibility, allowing the
reset ID to accommodate a broader range of values, including those
that may not fit into predefined enum values.

The use of u32 for reset ID enhances extensibility, especially for
hardware platforms or features where more granular control of reset
operations is required. By shifting to a general integer type, this
change reduces constraints and simplifies integration with other
system components that rely on non-enum-based reset IDs.

Signed-off-by: Ronak Jain &lt;ronak.jain@amd.com&gt;
Link: https://lore.kernel.org/r/20240830100042.3163511-1-ronak.jain@amd.com
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</content>
</entry>
<entry>
<title>firmware: xilinx: Add missing debug firmware interfaces</title>
<updated>2024-10-02T07:15:30Z</updated>
<author>
<name>Ronak Jain</name>
<email>ronak.jain@amd.com</email>
</author>
<published>2024-07-30T08:43:42Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=848f2bbb363d4cdb4202db328a103fd3c34e21a2'/>
<id>urn:sha1:848f2bbb363d4cdb4202db328a103fd3c34e21a2</id>
<content type='text'>
Add missing PM EEMI APIs interface in debug firmware driver.

The debugfs firmware driver interface is intended for testing and
debugging the EEMI APIs only. This interface does not contain any
checking regarding improper usage, and the number, type and valid
ranges of the arguments. This interface must be used with a lot of
care. In fact, accessing this interface during normal PM operation
will very likely cause unexpected problems.

The debugfs interface shouldn't be used in the production system and
hence it is disabled by default in defconfig.

Signed-off-by: Ronak Jain &lt;ronak.jain@amd.com&gt;
Signed-off-by: Radhey Shyam Pandey &lt;radhey.shyam.pandey@amd.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://lore.kernel.org/r/20240730084342.1683231-1-ronak.jain@amd.com
</content>
</entry>
<entry>
<title>firmware: xilinx: Add Pinctrl Get Attribute ID</title>
<updated>2024-10-01T12:03:40Z</updated>
<author>
<name>Sai Krishna Potthuri</name>
<email>sai.krishna.potthuri@amd.com</email>
</author>
<published>2024-09-06T11:01:12Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=86b9ce0a8a6cf9397503920cd5412d207a93fae9'/>
<id>urn:sha1:86b9ce0a8a6cf9397503920cd5412d207a93fae9</id>
<content type='text'>
Add Pinctrl Get Attribute ID to the query ids list.

Signed-off-by: Sai Krishna Potthuri &lt;sai.krishna.potthuri@amd.com&gt;
Link: https://lore.kernel.org/20240906110113.3154327-3-sai.krishna.potthuri@amd.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>firmware: imx: remove duplicate scmi_imx_misc_ctrl_get()</title>
<updated>2024-09-11T08:55:35Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2024-09-09T20:30:18Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=540c830212edc908361c39d40df21772a8bda308'/>
<id>urn:sha1:540c830212edc908361c39d40df21772a8bda308</id>
<content type='text'>
These two functions have a stub definition when CONFIG_IMX_SCMI_MISC_EXT
is not set, which conflict with the global definition:

In file included from drivers/firmware/imx/sm-misc.c:6:
include/linux/firmware/imx/sm.h:30:1: error: expected identifier or '(' before '{' token
   30 | {
      | ^
drivers/firmware/imx/sm-misc.c:26:5: error: redefinition of 'scmi_imx_misc_ctrl_get'
   26 | int scmi_imx_misc_ctrl_get(u32 id, u32 *num, u32 *val)
      |     ^~~~~~~~~~~~~~~~~~~~~~
include/linux/firmware/imx/sm.h:24:19: note: previous definition of 'scmi_imx_misc_ctrl_get' with type 'int(u32,  u32 *, u32 *)' {aka 'int(unsigned int,  unsigned int *, unsigned int *)'}
   24 | static inline int scmi_imx_misc_ctrl_get(u32 id, u32 *num, u32 *val)
      |                   ^~~~~~~~~~~~~~~~~~~~~~

There is no real need for the #ifdef, and removing this avoids
the build failure.

Fixes: 0b4f8a68b292 ("firmware: imx: Add i.MX95 MISC driver")
Link: https://lore.kernel.org/r/20240909203023.1275232-1-arnd@kernel.org
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>Merge tag 'qcom-drivers-for-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers</title>
<updated>2024-09-05T14:13:41Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2024-09-05T14:13:39Z</published>
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<id>urn:sha1:6d67480404db36a9d8b91cf4e45a7b42a230e1c9</id>
<content type='text'>
Qualcomm driver updates for v6.12

Support is added for making SCM driver configure the system either for a
full or minimal ramdump following a system crash. The ramdump mode is
changed from being enable-only to enable/disable as requested.

The QSEECOM uefisecapp interface is allow-listed on Surface Laptop 7 and
Lenovo Thinkpad T14s, providing EFI variable access.

The change to match the SMD RPM driver based on the SMD channel name is
reverted, in favor of stepping back to OF-based matching, as a means to
get module autoloading to work properly.

AOSS, APR, ICE, OCMEM, PBS and SMP2P drivers has error handling cleaned
up using scoped resources.

Trace events are added to the BWMON and SMP2P drivers, for better
insights into their operations.

The X1E LLCC configuration data is updated based on recommended values.

A number of platforms are added to the in-kernel PD-mapper.

SocInfo driver is extended with IDs from SM7325, QCS8275 and QCS8300
families.

* tag 'qcom-drivers-for-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (33 commits)
  firmware: qcom: scm: Allow QSEECOM on Surface Laptop 7 models
  dt-bindings: soc: qcom: qcom,pmic-glink: Document SM7325 compatible
  soc: qcom: pd_mapper: Add SM7325 compatible
  soc: qcom: socinfo: Add Soc IDs for SM7325 family
  dt-bindings: arm: qcom,ids: Add IDs for SM7325 family
  soc: qcom: socinfo: add QCS8275/QCS8300 SoC ID
  dt-bindings: arm: qcom,ids: add SoC ID for QCS8275/QCS8300
  soc: qcom: smp2p: use scoped device node handling to simplify error paths
  soc: qcom: pbs: use scoped device node handling to simplify error paths
  soc: qcom: ocmem: use scoped device node handling to simplify error paths
  soc: qcom: ice: use scoped device node handling to simplify error paths
  soc: qcom: aoss: simplify with scoped for each OF child loop
  soc: qcom: apr: simplify with scoped for each OF child loop
  soc: qcom: smd-rpm: add qcom,smd-rpm compatible
  dt-bindings: soc: qcom: smd-rpm: add generic compatibles
  Revert "soc: qcom: smd-rpm: Match rpmsg channel instead of compatible"
  firmware: qcom: scm: Add multiple download mode support
  firmware: qcom: scm: Refactor code to support multiple dload mode
  soc: qcom: pd_mapper: Add more older platforms without domains
  soc: qcom: pd_mapper: Add X1E80100
  ...

Link: https://lore.kernel.org/r/20240904193042.15118-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>firmware: imx: Add i.MX95 MISC driver</title>
<updated>2024-08-28T20:54:21Z</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2024-08-23T09:05:21Z</published>
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<id>urn:sha1:0b4f8a68b292e7ee82107b1ce15c3aad31c864b1</id>
<content type='text'>
The i.MX95 System manager exports SCMI MISC protocol for linux to do
various settings, such as set board gpio expander as wakeup source.

The driver is to add the support.

Reviewed-by: Cristian Marussi &lt;cristian.marussi@arm.com&gt;
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Message-Id: &lt;20240823-imx95-bbm-misc-v2-v8-5-e600ed9e9271@nxp.com&gt;
Signed-off-by: Sudeep Holla &lt;sudeep.holla@arm.com&gt;
</content>
</entry>
</feed>
