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<title>user/sven/linux.git/include/linux/firmware, branch v6.14.8</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v6.14.8</id>
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<updated>2025-04-25T08:50:49Z</updated>
<entry>
<title>firmware: cs_dsp: test_bin_error: Fix uninitialized data used as fw version</title>
<updated>2025-04-25T08:50:49Z</updated>
<author>
<name>Richard Fitzgerald</name>
<email>rf@opensource.cirrus.com</email>
</author>
<published>2025-04-10T13:21:29Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=d8832b03cad85a7e8110c96572d2b85bf8f15b5d'/>
<id>urn:sha1:d8832b03cad85a7e8110c96572d2b85bf8f15b5d</id>
<content type='text'>
[ Upstream commit 285b2c74cf9982e873ef82a2cb1328d9e9406f65 ]

Call cs_dsp_mock_xm_header_get_fw_version() to get the firmware version
from the dummy XM header data in cs_dsp_bin_err_test_common_init().

Make the same change to cs_dsp_bin_test_common_init() and remove the
cs_dsp_mock_xm_header_get_fw_version_from_regmap() function.

The code in cs_dsp_test_bin.c was correctly calling
cs_dsp_mock_xm_header_get_fw_version_from_regmap() to fetch the fw version
from a dummy header it wrote to XM registers. However in
cs_dsp_test_bin_error.c the test doesn't stuff a dummy header into XM, it
populates it the normal way using a wmfw file. It should have called
cs_dsp_mock_xm_header_get_fw_version() to get the data from its blob
buffer, but was calling cs_dsp_mock_xm_header_get_fw_version_from_regmap().
As nothing had been written to the registers this returned the value of
uninitialized data.

The only other use of cs_dsp_mock_xm_header_get_fw_version_from_regmap()
was cs_dsp_test_bin.c, but it doesn't need to use it. It already has a
blob buffer containing the dummy XM header so it can use
cs_dsp_mock_xm_header_get_fw_version() to read from that.

Fixes: cd8c058499b6 ("firmware: cs_dsp: Add KUnit testing of bin error cases")
Signed-off-by: Richard Fitzgerald &lt;rf@opensource.cirrus.com&gt;
Link: https://patch.msgid.link/20250410132129.1312541-1-rf@opensource.cirrus.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'soc-drivers-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc</title>
<updated>2025-01-24T22:56:59Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2025-01-24T22:56:59Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=f2ad904e923f70a80f478febf001f88dfd65a64c'/>
<id>urn:sha1:f2ad904e923f70a80f478febf001f88dfd65a64c</id>
<content type='text'>
Pull SoC driver updates from Arnd Bergmann:
 "These are changes to SoC specific drivers and DT bindings that don't
  have a separate subsystem tree, or that get grouped here for
  simplicity.

  Nothing out of the ordinary for the 6.14 release here:

   - Most of the updates are for Qualcomm specific drivers, adding
     support for additional SoCs in the exssting drivers, and support
     for wrapped encryption key access in the SCM firmware.

   - The Arm SCMI firmware code gains support for having multiple
     instances of firmware running, and better module auto loading.

   - A few minor updates for litex, samsung, ti, tegra, mediatek, imx
     and renesas platforms.

   - Reset controller updates for amlogic, to add support for the A1 soc
     and clean up the existing code.

   - Memory controller updates for ti davinci aemif, refactoring the
     code and adding a few interfaces to other drivers"

* tag 'soc-drivers-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (58 commits)
  drivers/soc/litex: Use devm_register_restart_handler()
  reset: amlogic: aux: drop aux registration helper
  reset: amlogic: aux: get regmap through parent device
  reset: amlogic: add support for A1 SoC in auxiliary reset driver
  dt-bindings: reset: add bindings for A1 SoC audio reset controller
  soc/tegra: fuse: Update Tegra234 nvmem keepout list
  soc/tegra: Fix spelling error in tegra234_lookup_slave_timeout()
  soc/tegra: cbb: Drop unnecessary debugfs error handling
  firmware: qcom: scm: add calls for wrapped key support
  soc: qcom: pd_mapper: Add SM7225 compatible
  dt-bindings: firmware: qcom,scm: Document ipq5424 SCM
  soc: qcom: llcc: Update configuration data for IPQ5424
  dt-bindings: cache: qcom,llcc: Add IPQ5424 compatible
  soc: mediatek: mtk-devapc: Fix leaking IO map on driver remove
  soc: mediatek: mtk-devapc: Fix leaking IO map on error paths
  firmware: qcom: scm: smc: Narrow 'mempool' variable scope
  firmware: qcom: scm: smc: Handle missing SCM device
  firmware: qcom: scm: Cleanup global '__scm' on probe failures
  firmware: qcom: scm: Fix missing read barrier in qcom_scm_get_tzmem_pool()
  firmware: qcom: scm: Fix missing read barrier in qcom_scm_is_available()
  ...
</content>
</entry>
<entry>
<title>firmware: qcom: scm: add calls for wrapped key support</title>
<updated>2025-01-08T23:11:07Z</updated>
<author>
<name>Gaurav Kashyap</name>
<email>quic_gaurkash@quicinc.com</email>
</author>
<published>2024-12-13T04:19:51Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=1d45a1cd9f3ae849db868e07e5fee5e5b37eff55'/>
<id>urn:sha1:1d45a1cd9f3ae849db868e07e5fee5e5b37eff55</id>
<content type='text'>
Add helper functions for the SCM calls required to support
hardware-wrapped inline storage encryption keys.  These SCM calls manage
wrapped keys via Qualcomm's Hardware Key Manager (HWKM), which can only
be accessed from TrustZone.

QCOM_SCM_ES_GENERATE_ICE_KEY and QCOM_SCM_ES_IMPORT_ICE_KEY create a new
long-term wrapped key, with the former making the hardware generate the
key and the latter importing a raw key.  QCOM_SCM_ES_PREPARE_ICE_KEY
converts the key to ephemerally-wrapped form so that it can be used for
inline storage encryption.  These are planned to be wired up to new
ioctls via the blk-crypto framework; see the proposed documentation for
the hardware-wrapped keys feature for more information.

Similarly there's also QCOM_SCM_ES_DERIVE_SW_SECRET which derives a
"software secret" from an ephemerally-wrapped key and will be wired up
to the corresponding operation in the blk_crypto_profile.

These will all be used by the ICE driver in drivers/soc/qcom/ice.c.

[EB: merged related patches, fixed error handling, fixed naming, fixed
     docs for size parameters, fixed qcom_scm_has_wrapped_key_support(),
     improved comments, improved commit message.]

Signed-off-by: Gaurav Kashyap &lt;quic_gaurkash@quicinc.com&gt;
Signed-off-by: Bartosz Golaszewski &lt;bartosz.golaszewski@linaro.org&gt;
Signed-off-by: Eric Biggers &lt;ebiggers@google.com&gt;
Link: https://lore.kernel.org/r/20241213041958.202565-9-ebiggers@kernel.org
Signed-off-by: Bjorn Andersson &lt;andersson@kernel.org&gt;
</content>
</entry>
<entry>
<title>firmware: cs_dsp: Add mock bin file generator for KUnit testing</title>
<updated>2024-12-13T13:14:40Z</updated>
<author>
<name>Richard Fitzgerald</name>
<email>rf@opensource.cirrus.com</email>
</author>
<published>2024-12-12T14:37:17Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=7c052c6615297ff32032105130cd5f02059f7ae4'/>
<id>urn:sha1:7c052c6615297ff32032105130cd5f02059f7ae4</id>
<content type='text'>
Add a mock firmware file that emulates what the firmware build tools
would normally create. This will be used by KUnit tests to generate a
test bin file.

The data payload in a bin is an opaque blob, so the mock bin only needs
to generate the appropriate file header and description block for each
payload blob.

Signed-off-by: Richard Fitzgerald &lt;rf@opensource.cirrus.com&gt;
Link: https://patch.msgid.link/20241212143725.1381013-5-rf@opensource.cirrus.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>firmware: cs_dsp: Add mock wmfw file generator for KUnit testing</title>
<updated>2024-12-13T13:14:39Z</updated>
<author>
<name>Richard Fitzgerald</name>
<email>rf@opensource.cirrus.com</email>
</author>
<published>2024-12-12T14:37:16Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=5cf1b7b471803f7cc654a29ee16cb085ad69c097'/>
<id>urn:sha1:5cf1b7b471803f7cc654a29ee16cb085ad69c097</id>
<content type='text'>
Add a mock firmware file that emulates what the firmware build tools
would normally create. This will be used by KUnit tests to generate a
test wmfw file.

Signed-off-by: Richard Fitzgerald &lt;rf@opensource.cirrus.com&gt;
Link: https://patch.msgid.link/20241212143725.1381013-4-rf@opensource.cirrus.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>firmware: cs_dsp: Add mock DSP memory map for KUnit testing</title>
<updated>2024-12-13T13:14:38Z</updated>
<author>
<name>Richard Fitzgerald</name>
<email>rf@opensource.cirrus.com</email>
</author>
<published>2024-12-12T14:37:15Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=41e78c0f44f97c958afcda3f82b23f4f4a05b968'/>
<id>urn:sha1:41e78c0f44f97c958afcda3f82b23f4f4a05b968</id>
<content type='text'>
Add helper functions to implement an emulation of the DSP memory map.

There are three main groups of functionality:

1. Define a mock cs_dsp_region table.
2. Calculate the addresses of memory and algorithms from the firmware
   header in XM.
3. Build a mock XM header in emulated XM.

Signed-off-by: Richard Fitzgerald &lt;rf@opensource.cirrus.com&gt;
Link: https://patch.msgid.link/20241212143725.1381013-3-rf@opensource.cirrus.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>firmware: cs_dsp: Add mock regmap for KUnit testing</title>
<updated>2024-12-13T13:14:37Z</updated>
<author>
<name>Richard Fitzgerald</name>
<email>rf@opensource.cirrus.com</email>
</author>
<published>2024-12-12T14:37:14Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=d54a3fc6bf3db0db0e16cfdf7f48a8bbb803f6b0'/>
<id>urn:sha1:d54a3fc6bf3db0db0e16cfdf7f48a8bbb803f6b0</id>
<content type='text'>
Add a mock regmap implementation to act as a simulated DSP for KUnit
testing. This is built as a utility module so that it could be used by
clients of cs_dsp to create a mock "DSP" for their own testing.

cs_dsp interacts with the DSP only through registers. Most of the
register space of the DSP is RAM. ADSP cores have a small set of control
registers. HALO Core DSPs have a much larger set of control registers but
only a small subset are used.

Most writes are "blind" in the sense that cs_dsp does not expect to
receive any sort of response from the DSP. So there isn't any need to
emulate a "DSP", only a set of registers that can be written and read
back.

The idea of the mock regmap is to use the cache to accumulate writes
which can then be tested against the values that are expected to be in
the registers.

Stray writes can be detected by dropping the cache entries for all
addresses that should have been written and then issuing a regcache_sync().
If this causes bus writes it means there were writes to unexpected
registers.

Signed-off-by: Richard Fitzgerald &lt;rf@opensource.cirrus.com&gt;
Link: https://patch.msgid.link/20241212143725.1381013-2-rf@opensource.cirrus.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'pinctrl-v6.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl</title>
<updated>2024-11-26T01:24:51Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2024-11-26T01:24:51Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=2d32fba02e0e5b67fb3a4ea51dde80c0db83f1c1'/>
<id>urn:sha1:2d32fba02e0e5b67fb3a4ea51dde80c0db83f1c1</id>
<content type='text'>
Pull pin control updates from Linus Walleij:
 "No core changes this time.

  New drivers:

   - Xlinix Versal pin control driver

   - Ocelot LAN969x pin control driver

   - T-Head TH1520 RISC-V SoC pin control driver

   - Qualcomm SM8750, IPQ5424, QCS8300, SAR2130P and QCS615 SoC pin
     control drivers

   - Qualcomm SM8750 LPASS (low power audio subsystem) pin control
     driver

   - Qualcomm PM8937 mixsig IC pin control support, GPIO and MPP
     (multi-purpose-pin)

   - Samsung Exynos8895 and Exynos9810 SoC pin control driver

   - SpacemiT K1 SoC pin control driver

   - Airhoa EN7581 IC pin control driver

  Improvements:

   - The Renesas subdriver now supports schmitt-trigger and open drain
     pin configurations if the hardware supports it

   - Support GPIOF and GPIOG banks in the Aspeed G6 SoC

   - Support the DSW community in the Intel Elkhartlake SoC"

* tag 'pinctrl-v6.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (105 commits)
  pinctrl: airoha: Use unsigned long for bit search
  pinctrl: k210: Undef K210_PC_DEFAULT
  pinctrl: qcom: spmi: fix debugfs drive strength
  pinctrl: qcom: Add sm8750 pinctrl driver
  dt-bindings: pinctrl: qcom: Add sm8750 pinctrl
  pinctrl: cy8c95x0: remove unneeded goto labels
  pinctrl: cy8c95x0: embed iterator to the for-loop
  pinctrl: cy8c95x0: Use temporary variable for struct device
  pinctrl: cy8c95x0: use flexible sleeping in reset function
  pinctrl: cy8c95x0: switch to using devm_regulator_get_enable()
  pinctrl: cy8c95x0: Use 2-argument strscpy()
  dt-bindings: pinctrl: sx150xq: allow gpio line naming
  pinctrl: single: add marvell,pxa1908-padconf compatible
  dt-bindings: pinctrl: pinctrl-single: add marvell,pxa1908-padconf compatible
  dt-bindings: pinctrl: correct typo of description for cv1800
  pinctrl: qcom: spmi-mpp: Add PM8937 compatible
  dt-bindings: pinctrl: qcom,pmic-mpp: Document PM8937 compatible
  pinctrl: qcom-pmic-gpio: add support for PM8937
  dt-bindings: pinctrl: qcom,pmic-gpio: add PM8937
  pinctrl: Use of_property_present() for non-boolean properties
  ...
</content>
</entry>
<entry>
<title>Merge tag 'qcom-drivers-for-6.13-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers</title>
<updated>2024-11-13T17:38:56Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2024-11-13T17:38:51Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=1876c788bba174660b538dcf5d1bc2b75d7f6d66'/>
<id>urn:sha1:1876c788bba174660b538dcf5d1bc2b75d7f6d66</id>
<content type='text'>
A few more Qualcomm driver updates for v6.13

Make the Adreno driver invoke the SMMU aperture setup firmware function,
which is required to allow the GPU to manage per-process page tables in
some firmware versions - as an example Rb3Gen2 has no GPU without this.

Add X1E Devkit to the list of devices that has functional EFI variable
access through the uefisecapp.

Flip the "manual slice configuration quirk" in the Qualcomm LLCC driver,
as this only applies to a single platform, and introduce support for
QCS8300, QCS615, SAR2130P, and SAR1130P.

Lastly, add IPQ5424 and IPQ5404 to the Qualcomm socinfo driver.

* tag 'qcom-drivers-for-6.13-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
  soc: qcom: ice: Remove the device_link field in qcom_ice
  drm/msm/adreno: Setup SMMU aparture for per-process page table
  firmware: qcom: scm: Introduce CP_SMMU_APERTURE_ID
  soc: qcom: socinfo: add IPQ5424/IPQ5404 SoC ID
  dt-bindings: arm: qcom,ids: add SoC ID for IPQ5424/IPQ5404
  soc: qcom: llcc: Flip the manual slice configuration condition
  dt-bindings: firmware: qcom,scm: Document sm8750 SCM
  firmware: qcom: uefisecapp: Allow X1E Devkit devices
  soc: qcom: llcc: Add LLCC configuration for the QCS8300 platform
  dt-bindings: cache: qcom,llcc: Document the QCS8300 LLCC
  soc: qcom: llcc: Add configuration data for QCS615
  dt-bindings: cache: qcom,llcc: Document the QCS615 LLCC
  soc: qcom: llcc: add support for SAR2130P and SAR1130P
  soc: qcom: llcc: use deciman integers for bit shift values
  dt-bindings: cache: qcom,llcc: document SAR2130P and SAR1130P

Link: https://lore.kernel.org/r/20241113032425.356306-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>firmware: qcom: scm: Introduce CP_SMMU_APERTURE_ID</title>
<updated>2024-11-11T18:03:26Z</updated>
<author>
<name>Bjorn Andersson</name>
<email>bjorn.andersson@oss.qualcomm.com</email>
</author>
<published>2024-11-10T17:33:40Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=1af75b2ad08bd5977c51c2d0fc11741a4c0a48d9'/>
<id>urn:sha1:1af75b2ad08bd5977c51c2d0fc11741a4c0a48d9</id>
<content type='text'>
The QCOM_SCM_SVC_MP service provides QCOM_SCM_MP_CP_SMMU_APERTURE_ID,
which is used to trigger the mapping of register banks into the SMMU
context for per-processes page tables to function (in case this isn't
statically setup by firmware).

This is necessary on e.g. QCS6490 Rb3Gen2, in order to avoid "CP | AHB
bus error"-errors from the GPU.

Introduce a function to allow the msm driver to invoke this call.

Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@oss.qualcomm.com&gt;
Reviewed-by: Rob Clark &lt;robdclark@gmail.com&gt;
Link: https://lore.kernel.org/r/20241110-adreno-smmu-aparture-v2-1-9b1fb2ee41d4@oss.qualcomm.com
Signed-off-by: Bjorn Andersson &lt;andersson@kernel.org&gt;
</content>
</entry>
</feed>
