user/sven/linux.git/include/linux/fsl_devices.h, branch v3.16.67

drivers: usb: fsl: Workaround for USB erratum-A005275

2015-10-28T10:33:15Z

commit f8786a91548df6930643a052e40e5c0b7a8403a5 upstream. Incoming packets in high speed are randomly corrupted by h/w resulting in multiple errors. This workaround makes FS as default mode in all affected socs by disabling HS chirp signalling.This errata does not affect FS and LS mode. Forces all HS devices to connect in FS mode for all socs affected by this erratum: P3041 and P2041 rev 1.0 and 1.1 P5020 and P5010 rev 1.0 and 2.0 P5040, P1010 and T4240 rev 1.0 Signed-off-by: Ramneek Mehresh Signed-off-by: Nikhil Badola Signed-off-by: Greg Kroah-Hartman Signed-off-by: Luis Henriques

drivers: usb :fsl: Implement Workaround for USB Erratum A007792

2015-10-28T10:33:14Z

commit 523f1dec58408b36e7683a3d61a0286eed1fc1c8 upstream. USB controller version-2.5 requires to enable internal UTMI phy and program PTS field in PORTSC register before asserting controller reset. This is must for successful resetting of the controller and subsequent enumeration of usb devices Signed-off-by: Nikhil Badola Signed-off-by: Suresh Gupta Signed-off-by: Greg Kroah-Hartman Signed-off-by: Luis Henriques

powerpc/usb: remove checking PHY_CLK_VALID for UTMI PHY

2012-09-24T20:42:45Z

PHY_CLK_VALID bit doesn't work properly with UTMI PHY. e.g. This bit is always zero on P5040, etc. There is no need to check this bit for UTMI PHY, just keep checking for ULPI PHY to prevent system hanging. This patch should be squashed into previous commit 3735ba8db8e6e "powerpc/usb: fix bug of CPU hang when missing USB PHY clock" Signed-off-by: Shengzhou Liu Signed-off-by: Greg Kroah-Hartman

fsl/usb: Add support for USB controller version 2.4

2012-09-21T16:43:55Z

Add support for USB controller version 2.4 Signed-off-by: Ramneek Mehresh Signed-off-by: Greg Kroah-Hartman

powerpc/usb: fix bug of CPU hang when missing USB PHY clock

2012-09-05T23:52:08Z

when missing USB PHY clock, kernel booting up will hang during USB initialization. We should check USBGP[PHY_CLK_VALID] bit to avoid CPU hanging in this case. Signed-off-by: Shengzhou Liu Signed-off-by: Greg Kroah-Hartman

fsl/usb: Add controller version based ULPI and UTMI phy support

2012-04-18T20:46:42Z

Add support for ULPI and UTMI PHYs based on usb controller version info read from device-tree Example of USB Controller versioning info: Version 1.2 and below : MPC8536, MPC8315, etc Version 1.6 : P1020, P1010, P2020, P5020, etc Version 2.2 : PSC9131, PSC9132, P3060, etc No changes for non-DT users Signed-off-by: Ramneek Mehresh Acked-by: Li Yang Signed-off-by: Greg Kroah-Hartman

USB: extend ehci-fsl and fsl_udc_core driver for OTG operation

2011-05-02T23:59:38Z

Signed-off-by: Anatolij Gustschin Cc: Li Yang Signed-off-by: Greg Kroah-Hartman

USB: ehci-fsl: add MPC5121E specific suspend and resume

2011-05-02T23:59:36Z

Signed-off-by: Anatolij Gustschin Signed-off-by: Greg Kroah-Hartman

mxc_udc: add workaround for ENGcm09152 for i.MX35

2010-10-22T17:22:17Z

this patch gives the possibility to workaround bug ENGcm09152 on i.MX35 when the hardware workaround is also implemented on the board. It covers the workaround described on page 25 of the following Errata : http://cache.freescale.com/files/dsp/doc/errata/IMX35CE.pdf Signed-off-by: Eric Bénard Signed-off-by: Greg Kroah-Hartman

USB: add USB EHCI support for MPC5121 SoC

2010-10-22T17:21:58Z

Extends FSL EHCI platform driver glue layer to support MPC5121 USB controllers. MPC5121 Rev 2.0 silicon EHCI registers are in big endian format. The appropriate flags are set using the information in the platform data structure. MPC83xx system interface registers are not available on MPC512x, so the access to these registers is isolated in MPC512x case. Furthermore the USB controller clocks must be enabled before 512x register accesses which is done by providing platform specific init callback. The MPC512x internal USB PHY doesn't provide supply voltage. For boards using different power switches allow specifying DRVVBUS and PWR_FAULT signal polarity of the MPC5121 internal PHY using "fsl,invert-drvvbus" and "fsl,invert-pwr-fault" properties in the device tree USB nodes. Adds documentation for this new device tree bindings. Signed-off-by: Anatolij Gustschin Cc: Grant Likely Signed-off-by: Greg Kroah-Hartman