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<title>user/sven/linux.git/include/linux/host1x.h, branch v4.14.219</title>
<subtitle>Linux Kernel
</subtitle>
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<updated>2017-06-15T12:25:38Z</updated>
<entry>
<title>gpu: host1x: Refactor channel allocation code</title>
<updated>2017-06-15T12:25:38Z</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2017-06-14T23:18:42Z</published>
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<id>urn:sha1:8474b02531c4881a762c52ef869c52429e38633f</id>
<content type='text'>
This is largely a rewrite of the Host1x channel allocation code, bringing
several changes:

- The previous code could deadlock due to an interaction
  between the 'reflock' mutex and CDMA timeout handling.
  This gets rid of the mutex.
- Support for more than 32 channels, required for Tegra186
- General refactoring, including better encapsulation
  of channel ownership handling into channel.c

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Reviewed-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Tested-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Correct swapped arguments in the is_addr_reg() definition</title>
<updated>2017-06-15T12:24:18Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2017-06-14T23:18:38Z</published>
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<id>urn:sha1:a2b78b0d53f0808ebc2a0368b589a5cb6b672294</id>
<content type='text'>
Arguments of the .is_addr_reg() are swapped in the definition of the
function, that is quite confusing.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Reviewed-by: Erik Faye-Lund &lt;kusmabite@gmail.com&gt;
Reviewed-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Forbid unrelated SETCLASS opcode in the firewall</title>
<updated>2017-06-15T12:23:50Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2017-06-14T23:18:37Z</published>
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<id>urn:sha1:0f563a4bf66e5182f0882efee398f7e6bc0bb1be</id>
<content type='text'>
Several channels could be made to write the same unit concurrently via
the SETCLASS opcode, trusting userspace is a bad idea. It should be
possible to drop the per-client channel reservation and add a per-unit
locking by inserting MLOCK's to the command stream to re-allow the
SETCLASS opcode, but it will be much more work. Let's forbid the
unit-unrelated class changes for now.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Reviewed-by: Erik Faye-Lund &lt;kusmabite@gmail.com&gt;
Reviewed-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Correct copying of waitchecks and disable them in the 'submit' IOCTL</title>
<updated>2017-06-15T12:16:37Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2017-06-14T23:18:27Z</published>
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<id>urn:sha1:d0fbbdff2e19aabccc1107b7e12ab9f3cbf626ef</id>
<content type='text'>
The waitchecks along with multiple syncpoints per submit are not ready
for use yet, let's forbid them for now.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Reviewed-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Flesh out kerneldoc</title>
<updated>2017-06-15T11:58:43Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2017-04-10T10:27:01Z</published>
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<id>urn:sha1:466749f13e33d892cf9263d7efbc0ea713c23ed7</id>
<content type='text'>
Improve kerneldoc for the public parts of the host1x infrastructure in
preparation for adding driver-specific part to the GPU documentation.

Acked-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Add VIC support</title>
<updated>2017-04-05T16:11:48Z</updated>
<author>
<name>Arto Merilainen</name>
<email>amerilainen@nvidia.com</email>
</author>
<published>2016-12-14T11:16:13Z</published>
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<id>urn:sha1:0ae797a8ba05a2354db5e81c1d7df04671dd1c25</id>
<content type='text'>
This patch adds support for Video Image Compositor engine which
can be used for 2d operations.

Signed-off-by: Andrew Chew &lt;achew@nvidia.com&gt;
Signed-off-by: Arto Merilainen &lt;amerilainen@nvidia.com&gt;
Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dsi: Enhance runtime power management</title>
<updated>2016-08-24T13:58:57Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2016-08-12T14:00:53Z</published>
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<id>urn:sha1:87904c3e82319cf2bad8d656d79c5030dab9490e</id>
<content type='text'>
The MIPI DSI output on Tegra SoCs requires some external logic to
calibrate the MIPI pads before a video signal can be transmitted. This
MIPI calibration logic requires to be powered on while the MIPI pads are
being used, which is currently done as part of the DSI driver's probe
implementation.

This is suboptimal because it will leave the MIPI calibration logic
powered up even if the DSI output is never used.

On Tegra114 and earlier this behaviour also causes the driver to hang
while trying to power up the MIPI calibration logic because the power
partition that contains the MIPI calibration logic will be powered on
by the display controller at output pipeline configuration time. Thus
the power up sequence for the MIPI calibration logic happens before
it's power partition is guaranteed to be enabled.

Fix this by splitting up the API into a request/free pair of functions
that manage the runtime dependency between the DSI and the calibration
modules (no registers are accessed) and a set of enable, calibrate and
disable functions that program the MIPI calibration logic at points in
time where the power partition is really enabled.

While at it, make sure that the runtime power management also works in
ganged mode, which is currently also broken.

Reported-by: Jonathan Hunter &lt;jonathanh@nvidia.com&gt;
Tested-by: Jonathan Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Export host1x_syncpt_read()</title>
<updated>2015-04-02T16:46:20Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-01-28T13:29:02Z</published>
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<id>urn:sha1:b4a20144e0c0a45431695fa5968ce2ed8c9ce6ca</id>
<content type='text'>
This function is used to read the current value of the syncpt and is
useful in situations where drivers don't schedule work and wait for the
syncpoint to increment. One particular use-case is using the syncpoint
as a VBLANK counter.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Provide a proper struct bus_type</title>
<updated>2015-01-27T09:09:14Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-12-18T14:29:14Z</published>
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<id>urn:sha1:f4c5cf88fbd50e4779042268947b2e2f90c20484</id>
<content type='text'>
Previously the struct bus_type exported by the host1x infrastructure was
only a very basic skeleton. Turn that implementation into a more full-
fledged bus to support proper probe ordering and power management.

Note that the bus infrastructure needs to be available before any of the
drivers can be registered. This is automatically ensured if all drivers
are built as loadable modules (via symbol dependencies). If all drivers
are built-in there are no such guarantees and the link order determines
the initcall ordering. Adjust drivers/gpu/Makefile to make sure that the
host1x bus infrastructure is initialized prior to any of its users (only
drm/tegra currently).

v2: Fix building host1x and tegra-drm as modules
    Reported-by: Dave Airlie &lt;airlied@gmail.com&gt;

Reviewed-by: Sean Paul &lt;seanpaul@chromium.org&gt;
Reviewed-by: Mark Zhang &lt;markz@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Call -&gt;remove() only when a device is bound</title>
<updated>2015-01-23T11:07:00Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-11-05T10:43:26Z</published>
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<id>urn:sha1:536e1715226c94037df12f7c6280cbe0f6009f92</id>
<content type='text'>
When a driver's -&gt;probe() function fails, the host1x bus must not call
its -&gt;remove() function because the driver will already have cleaned up
in the error handling path in -&gt;probe().

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
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