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<title>user/sven/linux.git/include/linux/intel-iommu.h, branch v3.10</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v3.10</id>
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<updated>2012-06-08T10:15:43Z</updated>
<entry>
<title>iommu/dmar: Reserve mmio space used by the IOMMU, if the BIOS forgets to</title>
<updated>2012-06-08T10:15:43Z</updated>
<author>
<name>Donald Dutile</name>
<email>ddutile@redhat.com</email>
</author>
<published>2012-06-04T21:29:02Z</published>
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<id>urn:sha1:6f5cf52114dd87f9ed091678f7dfc8ff21bbe2b3</id>
<content type='text'>
Intel-iommu initialization doesn't currently reserve the memory
used for the IOMMU registers. This can allow the pci resource
allocator to assign a device BAR to the same address as the
IOMMU registers. This can cause some not so nice side affects
when the driver ioremap's that region.

Introduced two helper functions to map &amp; unmap the IOMMU
registers as well as simplify the init and exit paths.

Signed-off-by: Donald Dutile &lt;ddutile@redhat.com&gt;
Acked-by: Chris Wright &lt;chrisw@redhat.com&gt;
Cc: iommu@lists.linux-foundation.org
Cc: suresh.b.siddha@intel.com
Cc: dwmw2@infradead.org
Link: http://lkml.kernel.org/r/1338845342-12464-3-git-send-email-ddutile@redhat.com
Signed-off-by: Ingo Molnar &lt;mingo@kernel.org&gt;
</content>
</entry>
<entry>
<title>Merge branch 'core-locking-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip</title>
<updated>2011-10-26T14:17:32Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2011-10-26T14:17:32Z</published>
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<id>urn:sha1:3cfef9524677a4ecb392d6fbffe6ebce6302f1d4</id>
<content type='text'>
* 'core-locking-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (27 commits)
  rtmutex: Add missing rcu_read_unlock() in debug_rt_mutex_print_deadlock()
  lockdep: Comment all warnings
  lib: atomic64: Change the type of local lock to raw_spinlock_t
  locking, lib/atomic64: Annotate atomic64_lock::lock as raw
  locking, x86, iommu: Annotate qi-&gt;q_lock as raw
  locking, x86, iommu: Annotate irq_2_ir_lock as raw
  locking, x86, iommu: Annotate iommu-&gt;register_lock as raw
  locking, dma, ipu: Annotate bank_lock as raw
  locking, ARM: Annotate low level hw locks as raw
  locking, drivers/dca: Annotate dca_lock as raw
  locking, powerpc: Annotate uic-&gt;lock as raw
  locking, x86: mce: Annotate cmci_discover_lock as raw
  locking, ACPI: Annotate c3_lock as raw
  locking, oprofile: Annotate oprofilefs lock as raw
  locking, video: Annotate vga console lock as raw
  locking, latencytop: Annotate latency_lock as raw
  locking, timer_stats: Annotate table_lock as raw
  locking, rwsem: Annotate inner lock as raw
  locking, semaphores: Annotate inner lock as raw
  locking, sched: Annotate thread_group_cputimer as raw
  ...

Fix up conflicts in kernel/posix-cpu-timers.c manually: making
cputimer-&gt;cputime a raw lock conflicted with the ABBA fix in commit
bcd5cff7216f ("cputimer: Cure lock inversion").
</content>
</entry>
<entry>
<title>iommu: Rename the DMAR and INTR_REMAP config options</title>
<updated>2011-09-21T08:22:03Z</updated>
<author>
<name>Suresh Siddha</name>
<email>suresh.b.siddha@intel.com</email>
</author>
<published>2011-08-24T00:05:25Z</published>
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<id>urn:sha1:d3f138106b4b40640dc667f0222fd9f137387b32</id>
<content type='text'>
Change the CONFIG_DMAR to CONFIG_INTEL_IOMMU to be consistent
with the other IOMMU options.

Rename the CONFIG_INTR_REMAP to CONFIG_IRQ_REMAP to match the
irq subsystem name.

And define the CONFIG_DMAR_TABLE for the common ACPI DMAR
routines shared by both CONFIG_INTEL_IOMMU and CONFIG_IRQ_REMAP.

Signed-off-by: Suresh Siddha &lt;suresh.b.siddha@intel.com&gt;
Cc: yinghai@kernel.org
Cc: youquan.song@intel.com
Cc: joerg.roedel@amd.com
Cc: tony.luck@intel.com
Cc: dwmw2@infradead.org
Link: http://lkml.kernel.org/r/20110824001456.558630224@sbsiddha-desk.sc.intel.com
Signed-off-by: Ingo Molnar &lt;mingo@elte.hu&gt;
</content>
</entry>
<entry>
<title>locking, x86, iommu: Annotate qi-&gt;q_lock as raw</title>
<updated>2011-09-13T09:12:20Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2011-07-19T15:02:07Z</published>
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<id>urn:sha1:3b8f40481513a7b6123def5a02db4cff96ae2198</id>
<content type='text'>
The qi-&gt;q_lock lock can be taken in atomic context and therefore
cannot be preempted on -rt - annotate it.

In mainline this change documents the low level nature of
the lock - otherwise there's no functional difference. Lockdep
and Sparse checking will work as usual.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Signed-off-by: Ingo Molnar &lt;mingo@elte.hu&gt;
</content>
</entry>
<entry>
<title>locking, x86, iommu: Annotate iommu-&gt;register_lock as raw</title>
<updated>2011-09-13T09:12:17Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2011-07-19T14:19:51Z</published>
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<id>urn:sha1:1f5b3c3fd2d73d6b30e9ef6dcbf131a791d5cbbd</id>
<content type='text'>
The iommu-&gt;register_lock can be taken in atomic context and therefore
must not be preempted on -rt - annotate it.

In mainline this change documents the low level nature of
the lock - otherwise there's no functional difference. Lockdep
and Sparse checking will work as usual.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Signed-off-by: Ingo Molnar &lt;mingo@elte.hu&gt;
</content>
</entry>
<entry>
<title>dmar: support for parsing Remapping Hardware Static Affinity structure</title>
<updated>2009-10-05T06:55:22Z</updated>
<author>
<name>Suresh Siddha</name>
<email>suresh.b.siddha@intel.com</email>
</author>
<published>2009-10-02T18:01:21Z</published>
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<id>urn:sha1:ee34b32d8c2950f66038c8975747ef9aec855289</id>
<content type='text'>
Add support for parsing Remapping Hardware Static Affinity (RHSA) structure.
This enables identifying the association between remapping hardware units and
the corresponding proximity domain. This enables to allocate transalation
structures closer to the remapping hardware unit.

Signed-off-by: Suresh Siddha &lt;suresh.b.siddha@intel.com&gt;
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>intel-iommu: Fix kernel hang if interrupt remapping disabled in BIOS</title>
<updated>2009-09-11T15:40:10Z</updated>
<author>
<name>Youquan Song</name>
<email>youquan.song@intel.com</email>
</author>
<published>2009-09-09T16:05:39Z</published>
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<id>urn:sha1:074835f0143b83845af5044af2739c52c9f53808</id>
<content type='text'>
BIOS clear DMAR table INTR_REMAP flag to disable interrupt remapping. Current
kernel only check interrupt remapping(IR) flag in DRHD's extended capability
register to decide interrupt remapping support or not. But IR flag will not
change when BIOS disable/enable interrupt remapping.

When user disable interrupt remapping in BIOS or BIOS often defaultly disable
interrupt remapping feature when BIOS is not mature.Though BIOS disable
interrupt remapping but intr_remapping_supported function will always report
to OS support interrupt remapping if VT-d2 chipset populated. On this
cases, kernel will continue enable interrupt remapping and result kernel panic.
This bug exist on almost all platforms with interrupt remapping support.

This patch add DMAR table INTR_REMAP flag check before enable interrupt
remapping.

Signed-off-by: Youquan Song &lt;youquan.song@intel.com&gt;
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>VT-d: support the device IOTLB</title>
<updated>2009-05-18T13:46:26Z</updated>
<author>
<name>Yu Zhao</name>
<email>yu.zhao@intel.com</email>
</author>
<published>2009-05-18T05:51:37Z</published>
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<id>urn:sha1:93a23a7271dfb811b3adb72779054c3a24433112</id>
<content type='text'>
Enable the device IOTLB (i.e. ATS) for both the bare metal and KVM
environments.

Signed-off-by: Yu Zhao &lt;yu.zhao@intel.com&gt;
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>VT-d: add device IOTLB invalidation support</title>
<updated>2009-05-18T13:45:13Z</updated>
<author>
<name>Yu Zhao</name>
<email>yu.zhao@intel.com</email>
</author>
<published>2009-05-18T05:51:35Z</published>
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<id>urn:sha1:6ba6c3a4cacfd68bf970e3e04e2ff0d66fa0f695</id>
<content type='text'>
Support device IOTLB invalidation to flush the translation cached
in the Endpoint.

Signed-off-by: Yu Zhao &lt;yu.zhao@intel.com&gt;
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>VT-d: parse ATSR in DMA Remapping Reporting Structure</title>
<updated>2009-05-18T13:45:09Z</updated>
<author>
<name>Yu Zhao</name>
<email>yu.zhao@intel.com</email>
</author>
<published>2009-05-18T05:51:34Z</published>
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<id>urn:sha1:aa5d2b515b6fca5f8a56eac84f7fa0a68c1ce9b7</id>
<content type='text'>
Parse the Root Port ATS Capability Reporting Structure in the DMA
Remapping Reporting Structure ACPI table.

Signed-off-by: Yu Zhao &lt;yu.zhao@intel.com&gt;
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
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