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<title>user/sven/linux.git/include/linux/intel-iommu.h, branch v4.4.2</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v4.4.2</id>
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<updated>2015-10-15T14:35:32Z</updated>
<entry>
<title>iommu/vt-d: Implement SVM_FLAG_PRIVATE_PASID to allocate unique PASIDs</title>
<updated>2015-10-15T14:35:32Z</updated>
<author>
<name>David Woodhouse</name>
<email>David.Woodhouse@intel.com</email>
</author>
<published>2015-10-15T12:59:14Z</published>
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<id>urn:sha1:569e4f7782fb92d0e1b395b5fb01de642dd74dcf</id>
<content type='text'>
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>iommu/vt-d: Add callback to device driver on page faults</title>
<updated>2015-10-15T14:35:28Z</updated>
<author>
<name>David Woodhouse</name>
<email>David.Woodhouse@intel.com</email>
</author>
<published>2015-10-13T16:18:10Z</published>
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<id>urn:sha1:0204a49609824163092c32a8aeb073f7e9acc76d</id>
<content type='text'>
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>iommu/vt-d: Implement page request handling</title>
<updated>2015-10-15T14:35:19Z</updated>
<author>
<name>David Woodhouse</name>
<email>David.Woodhouse@intel.com</email>
</author>
<published>2015-10-07T22:35:18Z</published>
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<id>urn:sha1:a222a7f0bb6c94c31cc9c755110593656f19de89</id>
<content type='text'>
Largely based on the driver-mode implementation by Jesse Barnes.

Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>iommu/vt-d: Generalise DMAR MSI setup to allow for page request events</title>
<updated>2015-10-15T12:22:41Z</updated>
<author>
<name>David Woodhouse</name>
<email>David.Woodhouse@intel.com</email>
</author>
<published>2015-10-07T14:37:03Z</published>
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<id>urn:sha1:1208225cf48fa3b170b6dfe7369f15c295260755</id>
<content type='text'>
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>iommu/vt-d: Add basic SVM PASID support</title>
<updated>2015-10-15T11:55:45Z</updated>
<author>
<name>David Woodhouse</name>
<email>David.Woodhouse@intel.com</email>
</author>
<published>2015-09-09T10:40:47Z</published>
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<id>urn:sha1:2f26e0a9c9860db290d63e9d85c2c8c09813677f</id>
<content type='text'>
This provides basic PASID support for endpoint devices, tested with a
version of the i915 driver.

Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>iommu/vt-d: Add initial support for PASID tables</title>
<updated>2015-10-15T10:24:51Z</updated>
<author>
<name>David Woodhouse</name>
<email>David.Woodhouse@intel.com</email>
</author>
<published>2015-03-24T14:54:56Z</published>
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<id>urn:sha1:8a94ade4ce6df22006b96c5c9a8d6d12fce67585</id>
<content type='text'>
Add CONFIG_INTEL_IOMMU_SVM, and allocate PASID tables on supported hardware.

Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>iommu/vt-d: Introduce intel_iommu=pasid28, and pasid_enabled() macro</title>
<updated>2015-10-15T10:24:45Z</updated>
<author>
<name>David Woodhouse</name>
<email>David.Woodhouse@intel.com</email>
</author>
<published>2015-09-09T10:58:59Z</published>
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<id>urn:sha1:ae853ddb9ad5e7c01cad3fbf016040acd961f407</id>
<content type='text'>
As long as we use an identity mapping to work around the worst of the
hardware bugs which caused us to defeature it and change the definition
of the capability bit, we *can* use PASID support on the devices which
advertised it in bit 28 of the Extended Capability Register.

Allow people to do so with 'intel_iommu=pasid28' on the command line.

Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>iommu/vt-d: Use plain writeq() for dmar_writeq() where available</title>
<updated>2015-10-13T19:48:23Z</updated>
<author>
<name>David Woodhouse</name>
<email>David.Woodhouse@intel.com</email>
</author>
<published>2015-10-13T19:48:21Z</published>
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<id>urn:sha1:50d3fb562561fcf5b745e71945834735d7386a1f</id>
<content type='text'>
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>iommu/vt-d: Split up iommu-&gt;domains array</title>
<updated>2015-08-12T14:23:33Z</updated>
<author>
<name>Joerg Roedel</name>
<email>jroedel@suse.de</email>
</author>
<published>2015-07-21T08:41:21Z</published>
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<id>urn:sha1:8bf478163e69e42973c7070179a11815139e5bf0</id>
<content type='text'>
This array is indexed by the domain-id and contains the
pointers to the domains attached to this iommu. Modern
systems support 65536 domain ids, so that this array has a
size of 512kb, per iommu.

This is a huge waste of space, as the array is usually
sparsely populated. This patch makes the array
two-dimensional and allocates the memory for the domain
pointers on-demand.

Signed-off-by: Joerg Roedel &lt;jroedel@suse.de&gt;
</content>
</entry>
<entry>
<title>Merge tag 'iommu-updates-v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu</title>
<updated>2015-06-24T01:27:19Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2015-06-24T01:27:19Z</published>
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<id>urn:sha1:6eae81a5e2d6646a61146501fd3032a340863c1d</id>
<content type='text'>
Pull IOMMU updates from Joerg Roedel:
 "This time with bigger changes than usual:

   - A new IOMMU driver for the ARM SMMUv3.

     This IOMMU is pretty different from SMMUv1 and v2 in that it is
     configured through in-memory structures and not through the MMIO
     register region.  The ARM SMMUv3 also supports IO demand paging for
     PCI devices with PRI/PASID capabilities, but this is not
     implemented in the driver yet.

   - Lots of cleanups and device-tree support for the Exynos IOMMU
     driver.  This is part of the effort to bring Exynos DRM support
     upstream.

   - Introduction of default domains into the IOMMU core code.

     The rationale behind this is to move functionalily out of the IOMMU
     drivers to common code to get to a unified behavior between
     different drivers.  The patches here introduce a default domain for
     iommu-groups (isolation groups).

     A device will now always be attached to a domain, either the
     default domain or another domain handled by the device driver.  The
     IOMMU drivers have to be modified to make use of that feature.  So
     long the AMD IOMMU driver is converted, with others to follow.

   - Patches for the Intel VT-d drvier to fix DMAR faults that happen
     when a kdump kernel boots.

     When the kdump kernel boots it re-initializes the IOMMU hardware,
     which destroys all mappings from the crashed kernel.  As this
     happens before the endpoint devices are re-initialized, any
     in-flight DMA causes a DMAR fault.  These faults cause PCI master
     aborts, which some devices can't handle properly and go into an
     undefined state, so that the device driver in the kdump kernel
     fails to initialize them and the dump fails.

     This is now fixed by copying over the mapping structures (only
     context tables and interrupt remapping tables) from the old kernel
     and keep the old mappings in place until the device driver of the
     new kernel takes over.  This emulates the the behavior without an
     IOMMU to the best degree possible.

   - A couple of other small fixes and cleanups"

* tag 'iommu-updates-v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (69 commits)
  iommu/amd: Handle large pages correctly in free_pagetable
  iommu/vt-d: Don't disable IR when it was previously enabled
  iommu/vt-d: Make sure copied over IR entries are not reused
  iommu/vt-d: Copy IR table from old kernel when in kdump mode
  iommu/vt-d: Set IRTA in intel_setup_irq_remapping
  iommu/vt-d: Disable IRQ remapping in intel_prepare_irq_remapping
  iommu/vt-d: Move QI initializationt to intel_setup_irq_remapping
  iommu/vt-d: Move EIM detection to intel_prepare_irq_remapping
  iommu/vt-d: Enable Translation only if it was previously disabled
  iommu/vt-d: Don't disable translation prior to OS handover
  iommu/vt-d: Don't copy translation tables if RTT bit needs to be changed
  iommu/vt-d: Don't do early domain assignment if kdump kernel
  iommu/vt-d: Allocate si_domain in init_dmars()
  iommu/vt-d: Mark copied context entries
  iommu/vt-d: Do not re-use domain-ids from the old kernel
  iommu/vt-d: Copy translation tables from old kernel
  iommu/vt-d: Detect pre enabled translation
  iommu/vt-d: Make root entry visible for hardware right after allocation
  iommu/vt-d: Init QI before root entry is allocated
  iommu/vt-d: Cleanup log messages
  ...
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