<feed xmlns='http://www.w3.org/2005/Atom'>
<title>user/sven/linux.git/include/linux/intel_rapl.h, branch v5.4.55</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v5.4.55</id>
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<updated>2019-07-15T09:42:31Z</updated>
<entry>
<title>intel_rapl: need linux/cpuhotplug.h for enum cpuhp_state</title>
<updated>2019-07-15T09:42:31Z</updated>
<author>
<name>Stephen Rothwell</name>
<email>sfr@canb.auug.org.au</email>
</author>
<published>2019-07-14T23:56:30Z</published>
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<id>urn:sha1:8da04e05cdfc715d414a1c5f8318c03030eb68fb</id>
<content type='text'>
Fixes: 7ebf8eff63b4 ("intel_rapl: introduce struct rapl_if_private")
Signed-off-by: Stephen Rothwell &lt;sfr@canb.auug.org.au&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>intel_rapl: support two power limits for every RAPL domain</title>
<updated>2019-07-11T13:08:58Z</updated>
<author>
<name>Zhang Rui</name>
<email>rui.zhang@intel.com</email>
</author>
<published>2019-07-10T13:44:32Z</published>
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<id>urn:sha1:0c2ddedd8bcb88c4100acb9e0fc5ac8752d09501</id>
<content type='text'>
RAPL MSR interface supports 2 power limits for package domain, and 1 power
limit for other domains, while RAPL MMIO interface supports 2 power limits
for both package and dram domains.
And when 2 power limits are supported, the FW_LOCK bit is in bit 63 of the
register, instead of bit 31.

Remove the assumption that only pakcage domain supports 2 power limits.
And allow the RAPL interface driver to specify the number of power limits
supported, for every single RAPL domain it owns..

Reviewed-by: Pandruvada, Srinivas &lt;srinivas.pandruvada@intel.com&gt;
Tested-by: Pandruvada, Srinivas &lt;srinivas.pandruvada@intel.com&gt;
Signed-off-by: Zhang Rui &lt;rui.zhang@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>intel_rapl: support 64 bit register</title>
<updated>2019-07-11T13:08:58Z</updated>
<author>
<name>Zhang Rui</name>
<email>rui.zhang@intel.com</email>
</author>
<published>2019-07-10T13:44:31Z</published>
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<id>urn:sha1:d978e755aabe215cb67bf713e103ed3916ec306d</id>
<content type='text'>
RAPL MMIO interface uses 64 bit registers, thus force use 64 bit register
for all the RAPL code.

Reviewed-by: Pandruvada, Srinivas &lt;srinivas.pandruvada@intel.com&gt;
Tested-by: Pandruvada, Srinivas &lt;srinivas.pandruvada@intel.com&gt;
Signed-off-by: Zhang Rui &lt;rui.zhang@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>intel_rapl: abstract RAPL common code</title>
<updated>2019-07-11T13:08:58Z</updated>
<author>
<name>Zhang Rui</name>
<email>rui.zhang@intel.com</email>
</author>
<published>2019-07-10T13:44:30Z</published>
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<id>urn:sha1:3382388d714891fc0f575926189f33d22e7c960b</id>
<content type='text'>
Split intel_rapl.c to intel_rapl_common.c and intel_rapl_msr.c, where
intel_rapl_common.c contains the common code that can be used by both MSR
and MMIO interface.
intel_rapl_msr.c contains the implementation of RAPL MSR interface.

Reviewed-by: Pandruvada, Srinivas &lt;srinivas.pandruvada@intel.com&gt;
Tested-by: Pandruvada, Srinivas &lt;srinivas.pandruvada@intel.com&gt;
Signed-off-by: Zhang Rui &lt;rui.zhang@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>intel_rapl: abstract register access operations</title>
<updated>2019-07-11T13:08:57Z</updated>
<author>
<name>Zhang Rui</name>
<email>rui.zhang@intel.com</email>
</author>
<published>2019-07-10T13:44:27Z</published>
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<id>urn:sha1:beea8df821d928e7755917da6c1e45d6afde5148</id>
<content type='text'>
MSR and MMIO RAPL interfaces have different ways to access the registers,
thus in order to abstract the register access operations, two callbacks,
.read_raw()/.write_raw() are introduced, and they should be implemented by
MSR RAPL and MMIO RAPL interface driver respectly.

This patch implements them for the MSR I/F only.

Reviewed-by: Pandruvada, Srinivas &lt;srinivas.pandruvada@intel.com&gt;
Tested-by: Pandruvada, Srinivas &lt;srinivas.pandruvada@intel.com&gt;
Signed-off-by: Zhang Rui &lt;rui.zhang@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>intel_rapl: abstract register address</title>
<updated>2019-07-11T13:08:57Z</updated>
<author>
<name>Zhang Rui</name>
<email>rui.zhang@intel.com</email>
</author>
<published>2019-07-10T13:44:26Z</published>
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<id>urn:sha1:7fde2712a7adab721eaabafbd8ff93dff3262d35</id>
<content type='text'>
MSR and MMIO RAPL interface have different sets of registers, thus the
RAPL register address should be obtained from interface specific
structure, i.e. struct rapl_if_private, instead.

Reviewed-by: Pandruvada, Srinivas &lt;srinivas.pandruvada@intel.com&gt;
Tested-by: Pandruvada, Srinivas &lt;srinivas.pandruvada@intel.com&gt;
Signed-off-by: Zhang Rui &lt;rui.zhang@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>intel_rapl: introduce struct rapl_if_private</title>
<updated>2019-07-11T13:08:57Z</updated>
<author>
<name>Zhang Rui</name>
<email>rui.zhang@intel.com</email>
</author>
<published>2019-07-10T13:44:25Z</published>
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<id>urn:sha1:7ebf8eff63b4f349e7b2ded6aa5036d94bdf94b9</id>
<content type='text'>
Introduce a new structure, rapl_if_private, to save the private data
for different RAPL Interface.

Reviewed-by: Pandruvada, Srinivas &lt;srinivas.pandruvada@intel.com&gt;
Tested-by: Pandruvada, Srinivas &lt;srinivas.pandruvada@intel.com&gt;
Signed-off-by: Zhang Rui &lt;rui.zhang@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>intel_rapl: introduce intel_rapl.h</title>
<updated>2019-07-11T13:08:57Z</updated>
<author>
<name>Zhang Rui</name>
<email>rui.zhang@intel.com</email>
</author>
<published>2019-07-10T13:44:24Z</published>
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<id>urn:sha1:ff956826a403f5cf189978d5ff6b3eb53aa11610</id>
<content type='text'>
Create a new header file for the common definitions that might be used
by different RAPL Interface.

Reviewed-by: Pandruvada, Srinivas &lt;srinivas.pandruvada@intel.com&gt;
Tested-by: Pandruvada, Srinivas &lt;srinivas.pandruvada@intel.com&gt;
Signed-off-by: Zhang Rui &lt;rui.zhang@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
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