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<title>user/sven/linux.git/include/linux/io-pgtable.h, branch v5.12.5</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v5.12.5</id>
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<updated>2021-02-12T14:27:17Z</updated>
<entry>
<title>Merge branches 'arm/renesas', 'arm/smmu', 'x86/amd', 'x86/vt-d' and 'core' into next</title>
<updated>2021-02-12T14:27:17Z</updated>
<author>
<name>Joerg Roedel</name>
<email>jroedel@suse.de</email>
</author>
<published>2021-02-12T14:27:17Z</published>
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<id>urn:sha1:45e606f2726926b04094e1c9bf809bca4884c57f</id>
<content type='text'>
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</entry>
<entry>
<title>iommu/io-pgtable-arm-v7s: Extend PA34 for MediaTek</title>
<updated>2021-02-01T11:31:17Z</updated>
<author>
<name>Yong Wu</name>
<email>yong.wu@mediatek.com</email>
</author>
<published>2021-01-11T11:18:51Z</published>
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<id>urn:sha1:40596d2f2b6075f6c33180b2f55c814ff4885475</id>
<content type='text'>
MediaTek extend the bit5 in lvl1 and lvl2 descriptor as PA34.

Signed-off-by: Yong Wu &lt;yong.wu@mediatek.com&gt;
Acked-by: Will Deacon &lt;will@kernel.org&gt;
Reviewed-by: Robin Murphy &lt;robin.murphy@arm.com&gt;
Reviewed-by: Tomasz Figa &lt;tfiga@chromium.org&gt;
Link: https://lore.kernel.org/r/20210111111914.22211-11-yong.wu@mediatek.com
Signed-off-by: Will Deacon &lt;will@kernel.org&gt;
</content>
</entry>
<entry>
<title>iommu/io-pgtable: Remove TLBI_ON_MAP quirk</title>
<updated>2021-01-28T21:05:11Z</updated>
<author>
<name>Robin Murphy</name>
<email>robin.murphy@arm.com</email>
</author>
<published>2021-01-27T16:29:29Z</published>
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<id>urn:sha1:3d5eab41451f8e28f3e45eef8f6b372bf56612fb</id>
<content type='text'>
IO_PGTABLE_QUIRK_TLBI_ON_MAP is now fully superseded by the
core API's iotlb_sync_map callback.

Signed-off-by: Robin Murphy &lt;robin.murphy@arm.com&gt;
Link: https://lore.kernel.org/r/5abb80bba3a7c371d5ffb7e59c05586deddb9a91.1611764372.git.robin.murphy@arm.com
[will: Remove unused 'iop' local variable from arm_v7s_map()]
Signed-off-by: Will Deacon &lt;will@kernel.org&gt;
</content>
</entry>
<entry>
<title>iommu/amd: Prepare for generic IO page table framework</title>
<updated>2021-01-28T15:51:17Z</updated>
<author>
<name>Suravee Suthikulpanit</name>
<email>suravee.suthikulpanit@amd.com</email>
</author>
<published>2020-12-15T07:36:54Z</published>
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<id>urn:sha1:c9b258c6be09283663c6851725b322568d867c0b</id>
<content type='text'>
Add initial hook up code to implement generic IO page table framework.

Signed-off-by: Suravee Suthikulpanit &lt;suravee.suthikulpanit@amd.com&gt;
Link: https://lore.kernel.org/r/20201215073705.123786-3-suravee.suthikulpanit@amd.com
Signed-off-by: Joerg Roedel &lt;jroedel@suse.de&gt;
</content>
</entry>
<entry>
<title>iommu/io-pgtable: Allow io_pgtable_tlb ops optional</title>
<updated>2021-01-27T12:32:27Z</updated>
<author>
<name>Yong Wu</name>
<email>yong.wu@mediatek.com</email>
</author>
<published>2021-01-07T12:29:07Z</published>
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<id>urn:sha1:77e0992aee4e980e8c553e512a5dfa3e704cf030</id>
<content type='text'>
This patch allows io_pgtable_tlb ops could be null since the IOMMU drivers
may use the tlb ops from iommu framework.

Signed-off-by: Yong Wu &lt;yong.wu@mediatek.com&gt;
Reviewed-by: Robin Murphy &lt;robin.murphy@arm.com&gt;
Acked-by: Will Deacon &lt;will@kernel.org&gt;
Link: https://lore.kernel.org/r/20210107122909.16317-6-yong.wu@mediatek.com
Signed-off-by: Will Deacon &lt;will@kernel.org&gt;
</content>
</entry>
<entry>
<title>iommu/io-pgtable: Remove tlb_flush_leaf</title>
<updated>2020-12-08T15:23:37Z</updated>
<author>
<name>Robin Murphy</name>
<email>robin.murphy@arm.com</email>
</author>
<published>2020-11-25T17:29:39Z</published>
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<id>urn:sha1:fefe8527a1e0e0014946c6b5b3b2e40cb32bb5d3</id>
<content type='text'>
The only user of tlb_flush_leaf is a particularly hairy corner of the
Arm short-descriptor code, which wants a synchronous invalidation to
minimise the races inherent in trying to split a large page mapping.
This is already far enough into "here be dragons" territory that no
sensible caller should ever hit it, and thus it really doesn't need
optimising. Although using tlb_flush_walk there may technically be
more heavyweight than needed, it does the job and saves everyone else
having to carry around useless baggage.

Signed-off-by: Robin Murphy &lt;robin.murphy@arm.com&gt;
Reviewed-by: Steven Price &lt;steven.price@arm.com&gt;
Link: https://lore.kernel.org/r/9844ab0c5cb3da8b2f89c6c2da16941910702b41.1606324115.git.robin.murphy@arm.com
Signed-off-by: Will Deacon &lt;will@kernel.org&gt;
</content>
</entry>
<entry>
<title>iommu/io-pgtable-arm: Add support to use system cache</title>
<updated>2020-11-25T12:39:09Z</updated>
<author>
<name>Sai Prakash Ranjan</name>
<email>saiprakash.ranjan@codeaurora.org</email>
</author>
<published>2020-11-25T07:00:11Z</published>
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<id>urn:sha1:e67890c97944b9962cf8c140a7f8077ed643b7d7</id>
<content type='text'>
Add a quirk IO_PGTABLE_QUIRK_ARM_OUTER_WBWA to override
the outer-cacheability attributes set in the TCR for a
non-coherent page table walker when using system cache.

Signed-off-by: Sai Prakash Ranjan &lt;saiprakash.ranjan@codeaurora.org&gt;
Link: https://lore.kernel.org/r/f818676b4a2a9ad1edb92721947d47db41ed6a7c.1606287059.git.saiprakash.ranjan@codeaurora.org
Signed-off-by: Will Deacon &lt;will@kernel.org&gt;
</content>
</entry>
<entry>
<title>iommu/io-pgtable: Add a domain attribute for pagetable configuration</title>
<updated>2020-11-25T12:39:09Z</updated>
<author>
<name>Sai Prakash Ranjan</name>
<email>saiprakash.ranjan@codeaurora.org</email>
</author>
<published>2020-11-25T07:00:10Z</published>
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<id>urn:sha1:a7656ecf825ac0434a5e7bf108ec1a56b65ee5e4</id>
<content type='text'>
Add a new iommu domain attribute DOMAIN_ATTR_IO_PGTABLE_CFG
for pagetable configuration which initially will be used to
set quirks like for system cache aka last level cache to be
used by client drivers like GPU to set right attributes for
caching the hardware pagetables into the system cache and
later can be extended to include other page table configuration
data.

Signed-off-by: Sai Prakash Ranjan &lt;saiprakash.ranjan@codeaurora.org&gt;
Link: https://lore.kernel.org/r/9190aa16f378fc0a7f8e57b2b9f60b033e7eeb4f.1606287059.git.saiprakash.ranjan@codeaurora.org
Signed-off-by: Will Deacon &lt;will@kernel.org&gt;
</content>
</entry>
<entry>
<title>iommu: Rename iommu_tlb_* functions to iommu_iotlb_*</title>
<updated>2020-09-04T09:16:09Z</updated>
<author>
<name>Tom Murphy</name>
<email>murphyt7@tcd.ie</email>
</author>
<published>2020-08-17T21:00:49Z</published>
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<id>urn:sha1:aae4c8e27bd7567132bb931488e2faf1a57c66e9</id>
<content type='text'>
To keep naming consistent we should stick with *iotlb*. This patch
renames a few remaining functions.

Signed-off-by: Tom Murphy &lt;murphyt7@tcd.ie&gt;
Link: https://lore.kernel.org/r/20200817210051.13546-1-murphyt7@tcd.ie
Signed-off-by: Joerg Roedel &lt;jroedel@suse.de&gt;
</content>
</entry>
<entry>
<title>iommu: Add gfp parameter to io_pgtable_ops-&gt;map()</title>
<updated>2020-07-24T12:29:47Z</updated>
<author>
<name>Baolin Wang</name>
<email>baolin.wang@linux.alibaba.com</email>
</author>
<published>2020-06-12T03:39:55Z</published>
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<id>urn:sha1:f34ce7a7018c2f71d78fc7f512f6daf01e487114</id>
<content type='text'>
Now the ARM page tables are always allocated by GFP_ATOMIC parameter,
but the iommu_ops-&gt;map() function has been added a gfp_t parameter by
commit 781ca2de89ba ("iommu: Add gfp parameter to iommu_ops::map"),
thus io_pgtable_ops-&gt;map() should use the gfp parameter passed from
iommu_ops-&gt;map() to allocate page pages, which can avoid wasting the
memory allocators atomic pools for some non-atomic contexts.

Signed-off-by: Baolin Wang &lt;baolin.wang@linux.alibaba.com&gt;
Acked-by: Will Deacon &lt;will@kernel.org&gt;
Link: https://lore.kernel.org/r/3093df4cb95497aaf713fca623ce4ecebb197c2e.1591930156.git.baolin.wang@linux.alibaba.com
Signed-off-by: Joerg Roedel &lt;jroedel@suse.de&gt;
</content>
</entry>
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