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<title>user/sven/linux.git/include/linux/iommu.h, branch v4.20</title>
<subtitle>Linux Kernel
</subtitle>
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<updated>2018-10-10T16:09:37Z</updated>
<entry>
<title>Merge branches 'arm/renesas', 'arm/smmu', 'ppc/pamu', 'x86/vt-d', 'x86/amd' and 'core' into next</title>
<updated>2018-10-10T16:09:37Z</updated>
<author>
<name>Joerg Roedel</name>
<email>jroedel@suse.de</email>
</author>
<published>2018-10-10T16:09:37Z</published>
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<id>urn:sha1:2f2fbfb71ecc221352d84ae6430b42031ae5b654</id>
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<entry>
<title>iommu/dma: Add support for non-strict mode</title>
<updated>2018-10-01T12:01:32Z</updated>
<author>
<name>Zhen Lei</name>
<email>thunder.leizhen@huawei.com</email>
</author>
<published>2018-09-20T16:10:22Z</published>
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<id>urn:sha1:2da274cdf998a1c12afa6b5975db2df1df01edf1</id>
<content type='text'>
With the flush queue infrastructure already abstracted into IOVA
domains, hooking it up in iommu-dma is pretty simple. Since there is a
degree of dependency on the IOMMU driver knowing what to do to play
along, we key the whole thing off a domain attribute which will be set
on default DMA ops domains to request non-strict invalidation. That way,
drivers can indicate the appropriate support by acknowledging the
attribute, and we can easily fall back to strict invalidation otherwise.

The flush queue callback needs a handle on the iommu_domain which owns
our cookie, so we have to add a pointer back to that, but neatly, that's
also sufficient to indicate whether we're using a flush queue or not,
and thus which way to release IOVAs. The only slight subtlety is
switching __iommu_dma_unmap() from calling iommu_unmap() to explicit
iommu_unmap_fast()/iommu_tlb_sync() so that we can elide the sync
entirely in non-strict mode.

Signed-off-by: Zhen Lei &lt;thunder.leizhen@huawei.com&gt;
[rm: convert to domain attribute, tweak comments and commit message]
Signed-off-by: Robin Murphy &lt;robin.murphy@arm.com&gt;
Signed-off-by: Will Deacon &lt;will.deacon@arm.com&gt;
</content>
</entry>
<entry>
<title>iommu: Remove .domain_{get,set}_windows</title>
<updated>2018-09-25T12:54:53Z</updated>
<author>
<name>Robin Murphy</name>
<email>robin.murphy@arm.com</email>
</author>
<published>2018-09-19T10:12:58Z</published>
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<id>urn:sha1:5131e08cd0f8a3faa30c1cdaf53940d6bce1715a</id>
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Since these are trivially handled by the .domain_{get,set}_attr
callbacks when relevant, we can streamline struct iommu_ops for
everyone.

Signed-off-by: Robin Murphy &lt;robin.murphy@arm.com&gt;
Signed-off-by: Joerg Roedel &lt;jroedel@suse.de&gt;
</content>
</entry>
<entry>
<title>iommu: Add fast hook for getting DMA domains</title>
<updated>2018-09-25T08:23:16Z</updated>
<author>
<name>Robin Murphy</name>
<email>robin.murphy@arm.com</email>
</author>
<published>2018-09-12T15:24:12Z</published>
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<id>urn:sha1:6af588fed39178c8e118fcf9cb6664e58a1fbe88</id>
<content type='text'>
While iommu_get_domain_for_dev() is the robust way for arbitrary IOMMU
API callers to retrieve the domain pointer, for DMA ops domains it
doesn't scale well for large systems and multi-queue devices, since the
momentary refcount adjustment will lead to exclusive cacheline contention
when multiple CPUs are operating in parallel on different mappings for
the same device.

In the case of DMA ops domains, however, this refcounting is actually
unnecessary, since they already imply that the group exists and is
managed by platform code and IOMMU internals (by virtue of
iommu_group_get_for_dev()) such that a reference will already be held
for the lifetime of the device. Thus we can avoid the bottleneck by
providing a fast lookup specifically for the DMA code to retrieve the
default domain it already knows it has set up - a simple read-only
dereference plays much nicer with cache-coherency protocols.

Signed-off-by: Robin Murphy &lt;robin.murphy@arm.com&gt;
Tested-by: Will Deacon &lt;will.deacon@arm.com&gt;
Signed-off-by: Joerg Roedel &lt;jroedel@suse.de&gt;
</content>
</entry>
<entry>
<title>iommu/arm-smmu: Add support for the fsl-mc bus</title>
<updated>2018-09-25T07:47:53Z</updated>
<author>
<name>Nipun Gupta</name>
<email>nipun.gupta@nxp.com</email>
</author>
<published>2018-09-10T13:49:18Z</published>
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<id>urn:sha1:eab03e2a1a3d9d354943aff5ae5e4254ee1ec967</id>
<content type='text'>
Implement bus specific support for the fsl-mc bus including
registering arm_smmu_ops and bus specific device add operations.

Signed-off-by: Nipun Gupta &lt;nipun.gupta@nxp.com&gt;
Reviewed-by: Robin Murphy &lt;robin.murphy@arm.com&gt;
Signed-off-by: Joerg Roedel &lt;jroedel@suse.de&gt;
</content>
</entry>
<entry>
<title>iommu: Remove the -&gt;map_sg indirection</title>
<updated>2018-08-08T09:06:20Z</updated>
<author>
<name>Christoph Hellwig</name>
<email>hch@lst.de</email>
</author>
<published>2018-07-30T07:36:26Z</published>
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<id>urn:sha1:d88e61faad526a5850e9330c846641b91cf971e7</id>
<content type='text'>
All iommu drivers use the default_iommu_map_sg implementation, and there
is no good reason to ever override it.  Just expose it as iommu_map_sg
directly and remove the indirection, specially in our post-spectre world
where indirect calls are horribly expensive.

Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Joerg Roedel &lt;jroedel@suse.de&gt;
</content>
</entry>
<entry>
<title>iommu: Enable debugfs exposure of IOMMU driver internals</title>
<updated>2018-07-06T12:06:30Z</updated>
<author>
<name>Gary R Hook</name>
<email>gary.hook@amd.com</email>
</author>
<published>2018-06-12T21:41:21Z</published>
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<id>urn:sha1:bad614b24293ae463e74d2465685f0e4e229baca</id>
<content type='text'>
Provide base enablement for using debugfs to expose internal data of an
IOMMU driver. When called, create the /sys/kernel/debug/iommu directory.

Emit a strong warning at boot time to indicate that this feature is
enabled.

This function is called from iommu_init, and creates the initial DebugFS
directory. Drivers may then call iommu_debugfs_new_driver_dir() to
instantiate a device-specific directory to expose internal data.
It will return a pointer to the new dentry structure created in
/sys/kernel/debug/iommu, or NULL in the event of a failure.

Since the IOMMU driver can not be removed from the running system, there
is no need for an "off" function.

Signed-off-by: Gary R Hook &lt;gary.hook@amd.com&gt;
Signed-off-by: Joerg Roedel &lt;jroedel@suse.de&gt;
</content>
</entry>
<entry>
<title>iommu: Do not return error code for APIs with size_t return type</title>
<updated>2018-02-13T18:31:20Z</updated>
<author>
<name>Suravee Suthikulpanit</name>
<email>suravee.suthikulpanit@amd.com</email>
</author>
<published>2018-02-05T10:45:53Z</published>
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<id>urn:sha1:c5611a8751e67595e4e7d3feaff3c900b92094b9</id>
<content type='text'>
Currently, iommu_unmap, iommu_unmap_fast and iommu_map_sg return
size_t.  However, some of the return values are error codes (&lt; 0),
which can be misinterpreted as large size. Therefore, returning size 0
instead to signify failure to map/unmap.

Cc: Joerg Roedel &lt;joro@8bytes.org&gt;
Cc: Alex Williamson &lt;alex.williamson@redhat.com&gt;
Signed-off-by: Suravee Suthikulpanit &lt;suravee.suthikulpanit@amd.com&gt;
Signed-off-by: Joerg Roedel &lt;jroedel@suse.de&gt;
</content>
</entry>
<entry>
<title>iommu: Fix comment for iommu_ops.map_sg</title>
<updated>2017-09-27T15:02:45Z</updated>
<author>
<name>Jean-Philippe Brucker</name>
<email>jean-philippe.brucker@arm.com</email>
</author>
<published>2017-09-26T18:32:52Z</published>
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<id>urn:sha1:50ce6312f293e129eedf2affc7bd791c71d8287e</id>
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The definition of map_sg was split during a recent addition to iommu_ops.
Put it back together.

Fixes: add02cfdc9bc ("iommu: Introduce Interface for IOMMU TLB Flushing")
Signed-off-by: Jean-Philippe Brucker &lt;jean-philippe.brucker@arm.com&gt;
Signed-off-by: Joerg Roedel &lt;jroedel@suse.de&gt;
</content>
</entry>
<entry>
<title>Merge branches 'arm/exynos', 'arm/renesas', 'arm/rockchip', 'arm/omap', 'arm/mediatek', 'arm/tegra', 'arm/qcom', 'arm/smmu', 'ppc/pamu', 'x86/vt-d', 'x86/amd', 's390' and 'core' into next</title>
<updated>2017-09-01T09:31:42Z</updated>
<author>
<name>Joerg Roedel</name>
<email>jroedel@suse.de</email>
</author>
<published>2017-09-01T09:31:42Z</published>
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