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<title>user/sven/linux.git/include/linux/irq.h, branch v4.10.4</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v4.10.4</id>
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<updated>2017-01-30T14:18:56Z</updated>
<entry>
<title>irqdomain: Avoid activating interrupts more than once</title>
<updated>2017-01-30T14:18:56Z</updated>
<author>
<name>Marc Zyngier</name>
<email>marc.zyngier@arm.com</email>
</author>
<published>2017-01-17T16:00:48Z</published>
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<id>urn:sha1:08d85f3ea99f1eeafc4e8507936190e86a16ee8c</id>
<content type='text'>
Since commit f3b0946d629c ("genirq/msi: Make sure PCI MSIs are
activated early"), we can end-up activating a PCI/MSI twice (once
at allocation time, and once at startup time).

This is normally of no consequences, except that there is some
HW out there that may misbehave if activate is used more than once
(the GICv3 ITS, for example, uses the activate callback
to issue the MAPVI command, and the architecture spec says that
"If there is an existing mapping for the EventID-DeviceID
combination, behavior is UNPREDICTABLE").

While this could be worked around in each individual driver, it may
make more sense to tackle the issue at the core level. In order to
avoid getting in that situation, let's have a per-interrupt flag
to remember if we have already activated that interrupt or not.

Fixes: f3b0946d629c ("genirq/msi: Make sure PCI MSIs are activated early")
Reported-and-tested-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Cc: stable@vger.kernel.org
Link: http://lkml.kernel.org/r/1484668848-24361-1-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;

</content>
</entry>
<entry>
<title>Merge branch 'irq/urgent' into irq/core</title>
<updated>2016-09-20T21:20:32Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2016-09-20T21:20:32Z</published>
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<id>urn:sha1:464b5847e61085f81bb99ce48eb427a0dc7617dc</id>
<content type='text'>
Merge urgent fixes so pending patches for 4.9 can be applied.
</content>
</entry>
<entry>
<title>genirq: Provide irq_gc_{lock_irqsave,unlock_irqrestore}() helpers</title>
<updated>2016-09-13T14:57:40Z</updated>
<author>
<name>Boris Brezillon</name>
<email>boris.brezillon@free-electrons.com</email>
</author>
<published>2016-09-13T13:58:28Z</published>
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<id>urn:sha1:ebf9ff753c041b296241990aef76163bbb2cc9c8</id>
<content type='text'>
Some irqchip drivers need to take the generic chip lock outside of the
irq context.

Provide the irq_gc_{lock_irqsave,unlock_irqrestore}() helpers to allow
one to disable irqs while entering a critical section protected by
gc-&gt;lock.

Note that we do not provide optimized version of these helpers for !SMP,
because they are not called from the hot-path.

[ tglx: Added a comment when these helpers should be [not] used ]

Signed-off-by: Boris Brezillon &lt;boris.brezillon@free-electrons.com&gt;
Cc: Jason Cooper &lt;jason@lakedaemon.net&gt;
Cc: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Cc: Nicolas Ferre &lt;nicolas.ferre@atmel.com&gt;
Cc: stable@vger.kernel.org
Cc: Alexandre Belloni &lt;alexandre.belloni@free-electrons.com&gt;
Link: http://lkml.kernel.org/r/1473775109-4192-1-git-send-email-boris.brezillon@free-electrons.com
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;

</content>
</entry>
<entry>
<title>genirq/generic_chip: Verify irqs_per_chip &lt;= 32</title>
<updated>2016-09-02T18:20:59Z</updated>
<author>
<name>Sebastian Frias</name>
<email>sf84@laposte.net</email>
</author>
<published>2016-08-16T14:05:08Z</published>
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<id>urn:sha1:f88eecfe2f22b2790e7527c0aaec14ea175919de</id>
<content type='text'>
Most (if not all) code here implicitly assumes that the maximum number of
IRQs per chip will be 32, and thus uses 'u32' or 'unsigned long' for many
tasks (for example "struct irq_data" declares its 'mask' field as 'u32',
and "struct irq_chip_generic" declares its 'installed' field as 'unsigned
long')

However, there is no check to verify that irqs_per_chip is &lt;= 32.  Hence,
calling irq_alloc_domain_generic_chips() with a bigger value will result in
unexpected results.

Provide a wrapper with a MAYBE_BUILD_BUG_ON(nrirqs &gt;= 32) to catch such
cases.

[ tglx: Reduced changelog to the essential information ]

Signed-off-by: Sebastian Frias &lt;sf84@laposte.net&gt;
Cc: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Cc: Mason &lt;slash.tmp@free.fr&gt;
Cc: Jason Cooper &lt;jason@lakedaemon.net&gt;
Link: http://lkml.kernel.org/r/57B31D94.5040701@laposte.net
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
</content>
</entry>
<entry>
<title>Merge branch 'irq/for-block' into irq/core</title>
<updated>2016-07-04T10:26:05Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2016-07-04T10:26:05Z</published>
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<id>urn:sha1:8658be133baa92c06b6d832a436d437deb2e2a22</id>
<content type='text'>
Pull the irq affinity managing code which is in a seperate branch for block
developers to pull.
</content>
</entry>
<entry>
<title>genirq: Add affinity hint to irq allocation</title>
<updated>2016-07-04T10:25:13Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2016-07-04T08:39:24Z</published>
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<id>urn:sha1:06ee6d571f0e350253a8fc3492316b2be007fae2</id>
<content type='text'>
Add an extra argument to the irq(domain) allocation functions, so we can hand
down affinity hints to the allocator. Thats necessary to implement proper
support for multiqueue devices.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: Christoph Hellwig &lt;hch@lst.de&gt;
Cc: linux-block@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: linux-nvme@lists.infradead.org
Cc: axboe@fb.com
Cc: agordeev@redhat.com
Link: http://lkml.kernel.org/r/1467621574-8277-4-git-send-email-hch@lst.de
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;

</content>
</entry>
<entry>
<title>genirq: Introduce IRQD_AFFINITY_MANAGED flag</title>
<updated>2016-07-04T10:25:13Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2016-07-04T08:39:23Z</published>
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<id>urn:sha1:9c2555835bb3d34dfac52a0be943dcc4bedd650f</id>
<content type='text'>
Interupts marked with this flag are excluded from user space interrupt
affinity changes. Contrary to the IRQ_NO_BALANCING flag, the kernel internal
affinity mechanism is not blocked.

This flag will be used for multi-queue device interrupts.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: Christoph Hellwig &lt;hch@lst.de&gt;
Cc: linux-block@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: linux-nvme@lists.infradead.org
Cc: axboe@fb.com
Cc: agordeev@redhat.com
Link: http://lkml.kernel.org/r/1467621574-8277-3-git-send-email-hch@lst.de
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;

</content>
</entry>
<entry>
<title>genirq: Add untracked irq handler</title>
<updated>2016-06-18T08:00:55Z</updated>
<author>
<name>Keith Busch</name>
<email>keith.busch@intel.com</email>
</author>
<published>2016-06-17T22:00:20Z</published>
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<id>urn:sha1:edd14cfebc4404698544d407ecf8eda6e19aa19e</id>
<content type='text'>
This adds a software irq handler for controllers that multiplex
interrupts from multiple devices, but don't know which device generated
the interrupt. For these devices, the irq handler that demuxes must
check every action for every software irq using the same h/w irq in order
to find out which device generated the interrupt. This will inevitably
trigger spurious interrupt detection if we are noting the irq.

The new irq handler does not track the handling for spurious interrupt
detection. An irq that uses this also won't get stats tracked since it
didn't generate the interrupt, nor added to randomness since they are
not random.

Signed-off-by: Keith Busch &lt;keith.busch@intel.com&gt;
Cc: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Cc: linux-pci@vger.kernel.org
Cc: Jon Derrick &lt;jonathan.derrick@intel.com&gt;
Link: http://lkml.kernel.org/r/1466200821-29159-1-git-send-email-keith.busch@intel.com
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;

</content>
</entry>
<entry>
<title>genirq: Add runtime power management support for IRQ chips</title>
<updated>2016-06-13T10:53:51Z</updated>
<author>
<name>Jon Hunter</name>
<email>jonathanh@nvidia.com</email>
</author>
<published>2016-06-07T15:12:29Z</published>
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<id>urn:sha1:be45beb2df6909d42a6b3b0052601b3eef878fc0</id>
<content type='text'>
Some IRQ chips may be located in a power domain outside of the CPU
subsystem and hence will require device specific runtime power
management. In order to support such IRQ chips, add a pointer for a
device structure to the irq_chip structure, and if this pointer is
populated by the IRQ chip driver and CONFIG_PM is selected in the kernel
configuration, then the pm_runtime_get/put APIs for this chip will be
called when an IRQ is requested/freed, respectively.

Reviewed-by: Kevin Hilman &lt;khilman@baylibre.com&gt;
Signed-off-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
</content>
</entry>
<entry>
<title>genirq: Allow the affinity of a percpu interrupt to be set/retrieved</title>
<updated>2016-05-02T11:42:51Z</updated>
<author>
<name>Marc Zyngier</name>
<email>marc.zyngier@arm.com</email>
</author>
<published>2016-04-11T08:57:52Z</published>
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<id>urn:sha1:222df54fd8b7641dcc81476f157806bb3144ee1d</id>
<content type='text'>
In order to prepare the genirq layer for the concept of partitionned
percpu interrupts, let's allow an affinity to be associated with
such an interrupt. We introduce:

- irq_set_percpu_devid_partition: flag an interrupt as a percpu-devid
  interrupt, and associate it with an affinity
- irq_get_percpu_devid_partition: allow the affinity of that interrupt
  to be retrieved.

This will allow a driver to discover which CPUs the per-cpu interrupt
can actually fire on.

Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Cc: Mark Rutland &lt;mark.rutland@arm.com&gt;
Cc: devicetree@vger.kernel.org
Cc: Jason Cooper &lt;jason@lakedaemon.net&gt;
Cc: Will Deacon &lt;will.deacon@arm.com&gt;
Cc: Rob Herring &lt;robh+dt@kernel.org&gt;
Link: http://lkml.kernel.org/r/1460365075-7316-3-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;

</content>
</entry>
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