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<title>user/sven/linux.git/include/linux/irqchip, branch v3.10.44</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v3.10.44</id>
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<updated>2013-04-11T10:39:00Z</updated>
<entry>
<title>Merge tag 'sunxi-cleanup-for-3.10' of git://github.com/mripard/linux into next/cleanup</title>
<updated>2013-04-11T10:39:00Z</updated>
<author>
<name>Olof Johansson</name>
<email>olof@lixom.net</email>
</author>
<published>2013-04-11T10:39:00Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=b9d5868e342a9802db7b299be511ac547ff1034d'/>
<id>urn:sha1:b9d5868e342a9802db7b299be511ac547ff1034d</id>
<content type='text'>
From Maxime Ripard:
Cleanups for Allwinner sunXi architecture:
  - Remove sunxi.dtsi
  - Switch to clocksource/irqchip device tree handlers
  - Cleanup the watchdog code

* tag 'sunxi-cleanup-for-3.10' of git://github.com/mripard/linux:
  ARM: sunxi: Rework the restart code
  irqchip: sunxi: Rename sunxi to sun4i
  irqchip: sunxi: Make use of the IRQCHIP_DECLARE macro
  clocksource: sunxi: Rename sunxi to sun4i
  clocksource: sunxi: make use of CLKSRC_OF
  clocksource: sunxi: Cleanup the timer code
  clocksource: make CLOCKSOURCE_OF_DECLARE type safe

Signed-off-by: Olof Johansson &lt;olof@lixom.net&gt;

Add/change conflict in drivers/clocksource/Makefile resolved.
</content>
</entry>
<entry>
<title>Merge tag 'mxs-cleanup-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/cleanup</title>
<updated>2013-04-09T13:29:52Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2013-04-09T13:29:52Z</published>
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<id>urn:sha1:92202876a3cc6b7fb0bbb52a5059e02c2c2e2186</id>
<content type='text'>
From Shawn Guo &lt;shawn.guo@linaro.org&gt;:

The mxs cleanup for 3.10:

* Clean up timer code and move it into drivers/clocksource
* Clean up icoll code and move it into drivers/irqchip
* Clean up clock code to not include &lt;mach/*&gt; headers
* Clean up rtc-stmp3xxx, mxs-lradc and mxs-saif to not include &lt;mach/*&gt;
  headers
* Clean up mach-mxs code to get it prepared for multiplatform support

* tag 'mxs-cleanup-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6: (26 commits)
  clocksource: mxs_timer: Add semicolon at end of line
  ARM: mxs: remove unused headers
  ARM: mxs: merge imx23 and imx28 into one machine_desc
  ARM: mxs: remove common.h
  ARM: mxs: move mxs_get_ocotp() into mach-mxs.c
  ARM: mxs: remove mm.c
  ARM: mxs: use debug_ll_io_init for low-level debug
  ARM: mxs: get ocotp base address from device tree
  ARM: mxs: remove system.c
  ARM: mxs: get reset address from device tree
  ARM: mxs: remove empty hardware.h
  ASoC: mxs-saif: remove mach header inclusion
  iio: mxs-lradc: remove unneeded mach header inclusion
  rtc: stmp3xxx: use stmp_reset_block() instead
  clk: mxs: remove the use of mach level IO accessor
  clk: mxs: get base address from device tree
  ARM: mxs: remove unneeded mach-types.h inclusion
  ARM: mxs: move icoll driver into drivers/irqchip
  ARM: mxs: call stmp_reset_block() in icoll
  ARM: mxs: get icoll base address from device tree
  ...

Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>irqchip: sunxi: Make use of the IRQCHIP_DECLARE macro</title>
<updated>2013-04-08T19:42:27Z</updated>
<author>
<name>Maxime Ripard</name>
<email>maxime.ripard@free-electrons.com</email>
</author>
<published>2013-03-10T14:54:46Z</published>
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<id>urn:sha1:f1dc6c4f77678979868fe220c6913890e13473d8</id>
<content type='text'>
This allows to remove some boilerplate code. At the same time, call the
set_handle_irq function in the initialization function of the irqchip,
so that we can remove it from the machine declaration.

Signed-off-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
</content>
</entry>
<entry>
<title>ARM: mxs: move icoll driver into drivers/irqchip</title>
<updated>2013-04-01T08:30:04Z</updated>
<author>
<name>Shawn Guo</name>
<email>shawn.guo@linaro.org</email>
</author>
<published>2013-03-25T13:34:51Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=6a8e95b071ecf7357d294782b6ef4e707ce0fbbd'/>
<id>urn:sha1:6a8e95b071ecf7357d294782b6ef4e707ce0fbbd</id>
<content type='text'>
Move icoll.c into drivers/irqchip as irq-mxs.c, and along with the
renaming, change the driver to use IRQCHIP_DECLARE.

Signed-off-by: Shawn Guo &lt;shawn.guo@linaro.org&gt;
</content>
</entry>
<entry>
<title>irqchip: gic: Perform the gic_secondary_init() call via CPU notifier</title>
<updated>2013-03-26T16:12:02Z</updated>
<author>
<name>Catalin Marinas</name>
<email>catalin.marinas@arm.com</email>
</author>
<published>2013-01-14T18:05:37Z</published>
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<id>urn:sha1:c0114709ed85a5693eb74acdfa03d94f7f12e5b8</id>
<content type='text'>
All the calls to gic_secondary_init() pass 0 as the first argument.
Since this function is called on each CPU when starting, it can be done
in a platform-independent way via a CPU notifier registered by the GIC
code.

Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Acked-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Acked-by: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
Acked-by: Santosh Shilimkar &lt;santosh.shilimkar@ti.com&gt;
Acked-by: Rob Herring &lt;rob.herring@calxeda.com&gt;
Acked-by: Simon Horman &lt;horms+renesas@verge.net.au&gt;
Tested-by: Simon Horman &lt;horms+renesas@verge.net.au&gt;
Acked-by: Srinidhi Kasagar &lt;srinidhi.kasagar@stericsson.com&gt;
Tested-by: Dinh Nguyen &lt;dinguyen@altera.com&gt;
Acked-by: Nicolas Pitre &lt;nico@linaro.org&gt;
Tested-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Cc: Russell King &lt;linux@arm.linux.org.uk&gt;
Cc: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: Kukjin Kim &lt;kgene.kim@samsung.com&gt;
Cc: Sascha Hauer &lt;kernel@pengutronix.de&gt;
Cc: David Brown &lt;davidb@codeaurora.org&gt;
Cc: Bryan Huntsman &lt;bryanh@codeaurora.org&gt;
Cc: Tony Lindgren &lt;tony@atomide.com&gt;
Cc: Magnus Damm &lt;magnus.damm@gmail.com&gt;
Cc: Shiraz Hashim &lt;shiraz.hashim@st.com&gt;
Cc: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Cc: Will Deacon &lt;will.deacon@arm.com&gt;
Cc: Kukjin Kim &lt;kgene.kim@samsung.com&gt;
Cc: Barry Song &lt;baohua.song@csr.com&gt;
</content>
</entry>
<entry>
<title>arm: Move chained_irq_(enter|exit) to a generic file</title>
<updated>2013-03-26T16:11:43Z</updated>
<author>
<name>Catalin Marinas</name>
<email>catalin.marinas@arm.com</email>
</author>
<published>2013-01-18T15:31:37Z</published>
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<id>urn:sha1:de88cbb7b244f3bcd61d49fd6dec35c19192545a</id>
<content type='text'>
These functions have been introduced by commit 10a8c383 (irq: introduce
entry and exit functions for chained handlers) in asm/mach/irq.h. This
patch moves them to linux/irqchip/chained_irq.h so that generic irqchip
drivers do not rely on architecture specific header files.

Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Tested-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Cc: Russell King &lt;linux@arm.linux.org.uk&gt;
Cc: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: Rob Herring &lt;rob.herring@calxeda.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'metag-v3.9-rc1-v4' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/metag</title>
<updated>2013-03-03T20:06:09Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2013-03-03T20:06:09Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=8fd5e7a2d9574b3cac1c9264ad1aed3b613ed6fe'/>
<id>urn:sha1:8fd5e7a2d9574b3cac1c9264ad1aed3b613ed6fe</id>
<content type='text'>
Pull new ImgTec Meta architecture from James Hogan:
 "This adds core architecture support for Imagination's Meta processor
  cores, followed by some later miscellaneous arch/metag cleanups and
  fixes which I kept separate to ease review:

   - Support for basic Meta 1 (ATP) and Meta 2 (HTP) core architecture
   - A few fixes all over, particularly for symbol prefixes
   - A few privilege protection fixes
   - Several cleanups (setup.c includes, split out a lot of
     metag_ksyms.c)
   - Fix some missing exports
   - Convert hugetlb to use vm_unmapped_area()
   - Copy device tree to non-init memory
   - Provide dma_get_sgtable()"

* tag 'metag-v3.9-rc1-v4' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/metag: (61 commits)
  metag: Provide dma_get_sgtable()
  metag: prom.h: remove declaration of metag_dt_memblock_reserve()
  metag: copy devicetree to non-init memory
  metag: cleanup metag_ksyms.c includes
  metag: move mm/init.c exports out of metag_ksyms.c
  metag: move usercopy.c exports out of metag_ksyms.c
  metag: move setup.c exports out of metag_ksyms.c
  metag: move kick.c exports out of metag_ksyms.c
  metag: move traps.c exports out of metag_ksyms.c
  metag: move irq enable out of irqflags.h on SMP
  genksyms: fix metag symbol prefix on crc symbols
  metag: hugetlb: convert to vm_unmapped_area()
  metag: export clear_page and copy_page
  metag: export metag_code_cache_flush_all
  metag: protect more non-MMU memory regions
  metag: make TXPRIVEXT bits explicit
  metag: kernel/setup.c: sort includes
  perf: Enable building perf tools for Meta
  metag: add boot time LNKGET/LNKSET check
  metag: add __init to metag_cache_probe()
  ...
</content>
</entry>
<entry>
<title>metag: Internal and external irqchips</title>
<updated>2013-03-02T20:09:48Z</updated>
<author>
<name>James Hogan</name>
<email>james.hogan@imgtec.com</email>
</author>
<published>2012-10-09T09:54:47Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=5698c50d9da4ab2f57d98c64ea97675dcaf2a608'/>
<id>urn:sha1:5698c50d9da4ab2f57d98c64ea97675dcaf2a608</id>
<content type='text'>
Meta core internal interrupts (from HWSTATMETA and friends) are vectored
onto the TR1 core trigger for the current thread. This is demultiplexed
in irq-metag.c to individual Linux IRQs for each internal interrupt.

External SoC interrupts (from HWSTATEXT and friends) are vectored onto
the TR2 core trigger for the current thread. This is demultiplexed in
irq-metag-ext.c to individual Linux IRQs for each external SoC interrupt.
The external irqchip has devicetree bindings for configuring the number
of irq banks and the type of masking available.

Signed-off-by: James Hogan &lt;james.hogan@imgtec.com&gt;
Cc: Arnd Bergmann &lt;arnd@arndb.de&gt;
Cc: Grant Likely &lt;grant.likely@secretlab.ca&gt;
Cc: Rob Herring &lt;rob.herring@calxeda.com&gt;
Cc: Rob Landley &lt;rob@landley.net&gt;
Cc: Dom Cobley &lt;popcornmix@gmail.com&gt;
Cc: Simon Arlott &lt;simon@fire.lp0.eu&gt;
Cc: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
Cc: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
Cc: devicetree-discuss@lists.ozlabs.org
Cc: linux-doc@vger.kernel.org
</content>
</entry>
<entry>
<title>ARM: gic: add __ASSEMBLY__ guard to C definitions</title>
<updated>2013-02-11T18:58:34Z</updated>
<author>
<name>Marc Zyngier</name>
<email>marc.zyngier@arm.com</email>
</author>
<published>2013-01-24T13:39:43Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=a96ab03917dcf4c9477d03b31e8d74779bca1074'/>
<id>urn:sha1:a96ab03917dcf4c9477d03b31e8d74779bca1074</id>
<content type='text'>
The GIC include file being used by some of the KVM assembly code,
wrap the C definitions with a #ifdef __ASSEMBLY__ guard.

Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
</content>
</entry>
<entry>
<title>ARM: gic: define GICH offsets for VGIC support</title>
<updated>2013-02-11T18:58:23Z</updated>
<author>
<name>Marc Zyngier</name>
<email>marc.zyngier@arm.com</email>
</author>
<published>2013-01-22T00:36:11Z</published>
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<id>urn:sha1:fdf77a72ec110572ac033d499c8be8b389c05740</id>
<content type='text'>
The GICH_* constants are defined by the GIC HW spec, and even though
they only be used by KVM to begin with, define them generically in gic.h.

Reviewed-by: Will Deacon &lt;will.deacon@arm.com&gt;
Signed-off-by: Christoffer Dall &lt;c.dall@virtualopensystems.com&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
</content>
</entry>
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