<feed xmlns='http://www.w3.org/2005/Atom'>
<title>user/sven/linux.git/include/linux/irqchip, branch v5.10.230</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v5.10.230</id>
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<updated>2024-10-22T13:39:29Z</updated>
<entry>
<title>irqchip/gic-v4: Don't allow a VMOVP on a dying VPE</title>
<updated>2024-10-22T13:39:29Z</updated>
<author>
<name>Marc Zyngier</name>
<email>maz@kernel.org</email>
</author>
<published>2024-10-02T20:49:59Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=b7d7b7fc876f836f40bf48a87e07ea18756ba196'/>
<id>urn:sha1:b7d7b7fc876f836f40bf48a87e07ea18756ba196</id>
<content type='text'>
commit 1442ee0011983f0c5c4b92380e6853afb513841a upstream.

Kunkun Jiang reported that there is a small window of opportunity for
userspace to force a change of affinity for a VPE while the VPE has already
been unmapped, but the corresponding doorbell interrupt still visible in
/proc/irq/.

Plug the race by checking the value of vmapp_count, which tracks whether
the VPE is mapped ot not, and returning an error in this case.

This involves making vmapp_count common to both GICv4.1 and its v4.0
ancestor.

Fixes: 64edfaa9a234 ("irqchip/gic-v4.1: Implement the v4.1 flavour of VMAPP")
Reported-by: Kunkun Jiang &lt;jiangkunkun@huawei.com&gt;
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/c182ece6-2ba0-ce4f-3404-dba7a3ab6c52@huawei.com
Link: https://lore.kernel.org/all/20241002204959.2051709-1-maz@kernel.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>include/: replace HTTP links with HTTPS ones</title>
<updated>2020-08-12T17:57:59Z</updated>
<author>
<name>Alexander A. Klimov</name>
<email>grandmaster@al2klimov.de</email>
</author>
<published>2020-08-12T01:34:19Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=7f317d34906c1033f0752fc137dda04e43979bb8'/>
<id>urn:sha1:7f317d34906c1033f0752fc137dda04e43979bb8</id>
<content type='text'>
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.

Signed-off-by: Alexander A. Klimov &lt;grandmaster@al2klimov.de&gt;
Signed-off-by: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Reviewed-by: Kees Cook &lt;keescook@chromium.org&gt;
Link: http://lkml.kernel.org/r/20200726110117.16346-1-grandmaster@al2klimov.de
Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</content>
</entry>
<entry>
<title>irqchip: irq-bcm2836.h: drop a duplicated word</title>
<updated>2020-07-27T07:55:03Z</updated>
<author>
<name>Randy Dunlap</name>
<email>rdunlap@infradead.org</email>
</author>
<published>2020-07-19T00:28:53Z</published>
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<id>urn:sha1:b7640d765dbbde794c49198c9851f6026fb6e43e</id>
<content type='text'>
Drop the repeated word "the" in a comment.

Signed-off-by: Randy Dunlap &lt;rdunlap@infradead.org&gt;
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
Cc: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: Jason Cooper &lt;jason@lakedaemon.net&gt;
Cc: Marc Zyngier &lt;maz@kernel.org&gt;
Link: https://lore.kernel.org/r/20200719002853.20419-1-rdunlap@infradead.org
</content>
</entry>
<entry>
<title>irqchip/gic-v3: Remove unused register definition</title>
<updated>2020-07-27T07:55:03Z</updated>
<author>
<name>Zenghui Yu</name>
<email>yuzenghui@huawei.com</email>
</author>
<published>2020-06-30T13:41:26Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=6d4c4479f80141a2a24ac798a86942b1225206df'/>
<id>urn:sha1:6d4c4479f80141a2a24ac798a86942b1225206df</id>
<content type='text'>
[maz: The GICv3 spec has evolved quite a bit since the draft the Linux
driver was written against, and some register definitions are simply gone]

As per the GICv3 specification, GIC{D,R}_SEIR are not assigned and the
locations (0x0068) are actually Reserved. GICR_MOV{LPI,ALL}R are two IMP
DEF registers and might be defined by some specific micro-architecture.

As they're not used anywhere in the kernel, just drop all of them.

Signed-off-by: Zenghui Yu &lt;yuzenghui@huawei.com&gt;
[maz: added context explaination]
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
Link: https://lore.kernel.org/r/20200630134126.880-1-yuzenghui@huawei.com
</content>
</entry>
<entry>
<title>irqchip/vic: Cut down the external API</title>
<updated>2020-06-27T10:54:54Z</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2020-06-07T21:51:24Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=b0b92ab6a86e59779c2b17c5f611b04120fdfbb6'/>
<id>urn:sha1:b0b92ab6a86e59779c2b17c5f611b04120fdfbb6</id>
<content type='text'>
There are registers and functions in the header file
that are only used inside the driver. Move these into
the driver.

Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
Link: https://lore.kernel.org/r/20200607215124.48638-2-linus.walleij@linaro.org
</content>
</entry>
<entry>
<title>irqchip/vic: Drop cascaded intialization call</title>
<updated>2020-06-27T10:54:47Z</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2020-06-07T21:51:23Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=adf4f9d49c74a812757c5c67879ece0e54b75417'/>
<id>urn:sha1:adf4f9d49c74a812757c5c67879ece0e54b75417</id>
<content type='text'>
We got rid of the last user of the cascaded intialization
from board files so drop this API.

Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
Link: https://lore.kernel.org/r/20200607215124.48638-1-linus.walleij@linaro.org
</content>
</entry>
<entry>
<title>irqchip/gic-v4.1: Add support for VPENDBASER's Dirty+Valid signaling</title>
<updated>2020-04-16T09:28:12Z</updated>
<author>
<name>Marc Zyngier</name>
<email>maz@kernel.org</email>
</author>
<published>2020-04-10T10:13:26Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=96806229ca033f85310bc5c203410189f8a1d2ee'/>
<id>urn:sha1:96806229ca033f85310bc5c203410189f8a1d2ee</id>
<content type='text'>
When a vPE is made resident, the GIC starts parsing the virtual pending
table to deliver pending interrupts. This takes place asynchronously,
and can at times take a long while. Long enough that the vcpu enters
the guest and hits WFI before any interrupt has been signaled yet.
The vcpu then exits, blocks, and now gets a doorbell. Rince, repeat.

In order to avoid the above, a (optional on GICv4, mandatory on v4.1)
feature allows the GIC to feedback to the hypervisor whether it is
done parsing the VPT by clearing the GICR_VPENDBASER.Dirty bit.
The hypervisor can then wait until the GIC is ready before actually
running the vPE.

Plug the detection code as well as polling on vPE schedule. While
at it, tidy-up the kernel message that displays the GICv4 optional
features.

Reviewed-by: Zenghui Yu &lt;yuzenghui@huawei.com&gt;
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
</content>
</entry>
<entry>
<title>Merge branch 'irq/gic-v4.1' into irq/irqchip-next</title>
<updated>2020-03-24T12:43:47Z</updated>
<author>
<name>Marc Zyngier</name>
<email>maz@kernel.org</email>
</author>
<published>2020-03-24T12:43:47Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=771df8cf0bc3a9a94bc16a58da136cad186cea27'/>
<id>urn:sha1:771df8cf0bc3a9a94bc16a58da136cad186cea27</id>
<content type='text'>
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
</content>
</entry>
<entry>
<title>irqchip/gic-v4.1: Add VSGI property setup</title>
<updated>2020-03-24T12:15:51Z</updated>
<author>
<name>Marc Zyngier</name>
<email>maz@kernel.org</email>
</author>
<published>2020-03-04T20:33:22Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=d50676f5ce8481b98f9bbc1514b5d3f8747dd3c2'/>
<id>urn:sha1:d50676f5ce8481b98f9bbc1514b5d3f8747dd3c2</id>
<content type='text'>
Add the SGI configuration entry point for KVM to use.

Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
Reviewed-by: Zenghui Yu &lt;yuzenghui@huawei.com&gt;
Link: https://lore.kernel.org/r/20200304203330.4967-16-maz@kernel.org
</content>
</entry>
<entry>
<title>irqchip/gic-v4.1: Add VSGI allocation/teardown</title>
<updated>2020-03-24T12:15:51Z</updated>
<author>
<name>Marc Zyngier</name>
<email>maz@kernel.org</email>
</author>
<published>2020-03-04T20:33:21Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=6d31b6ff985dbd144b2c4d519cf573b8f81865d9'/>
<id>urn:sha1:6d31b6ff985dbd144b2c4d519cf573b8f81865d9</id>
<content type='text'>
Allocate per-VPE SGIs when initializing the GIC-specific part of the
VPE data structure.

Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
Reviewed-by: Zenghui Yu &lt;yuzenghui@huawei.com&gt;
Link: https://lore.kernel.org/r/20200304203330.4967-15-maz@kernel.org
</content>
</entry>
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