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<title>user/sven/linux.git/include/linux/libnvdimm.h, branch v4.14.115</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v4.14.115</id>
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<updated>2017-08-31T22:05:10Z</updated>
<entry>
<title>libnvdimm, nd_blk: remove mmio_flush_range()</title>
<updated>2017-08-31T22:05:10Z</updated>
<author>
<name>Robin Murphy</name>
<email>robin.murphy@arm.com</email>
</author>
<published>2017-08-31T11:27:09Z</published>
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<id>urn:sha1:5deb67f77a266010e2c10fb124b7516d0d258ce8</id>
<content type='text'>
mmio_flush_range() suffers from a lack of clearly-defined semantics,
and is somewhat ambiguous to port to other architectures where the
scope of the writeback implied by "flush" and ordering might matter,
but MMIO would tend to imply non-cacheable anyway. Per the rationale
in 67a3e8fe9015 ("nd_blk: change aperture mapping from WC to WB"), the
only existing use is actually to invalidate clean cache lines for
ARCH_MEMREMAP_PMEM type mappings *without* writeback. Since the recent
cleanup of the pmem API, that also now happens to be the exact purpose
of arch_invalidate_pmem(), which would be a far more well-defined tool
for the job.

Rather than risk potentially inconsistent implementations of
mmio_flush_range() for the sake of one callsite, streamline things by
removing it entirely and instead move the ARCH_MEMREMAP_PMEM related
definitions up to the libnvdimm level, so they can be shared by NFIT
as well. This allows NFIT to be enabled for arm64.

Signed-off-by: Robin Murphy &lt;robin.murphy@arm.com&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>nfit, libnvdimm, region: export 'position' in mapping info</title>
<updated>2017-08-05T00:20:16Z</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2017-08-05T00:20:16Z</published>
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<id>urn:sha1:401c0a19c6c22efcaff85d5a64a396f9130da2ca</id>
<content type='text'>
It is useful to be able to know the position of a DIMM in an
interleave-set. Consider the case where the order of the DIMMs changes
causing a namespace to be invalidated because the interleave-set cookie no
longer matches. If the before and after state of each DIMM position is
known this state debugged by the system owner.

Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'for-4.13/dax' into libnvdimm-for-next</title>
<updated>2017-07-03T23:54:58Z</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2017-07-03T23:54:58Z</published>
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<id>urn:sha1:9d92573fff3ec70785ef1815cc80573f70e7a921</id>
<content type='text'>
</content>
</entry>
<entry>
<title>libnvdimm, acpi, nfit: Add bus level dsm mask for pass thru.</title>
<updated>2017-07-01T15:49:59Z</updated>
<author>
<name>Jerry Hoemann</name>
<email>jerry.hoemann@hpe.com</email>
</author>
<published>2017-07-01T03:53:24Z</published>
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<id>urn:sha1:7db5bb33add5afe6c64e00516b0c928bfc937466</id>
<content type='text'>
Add a bus level dsm_mask to nvdimm_bus_descriptor to allow the passthru
calling mechanism to specify a different mask from the cmd_mask.

Populate bus_dsm_mask and use it to filter dsm calls that user can
make through the pass thru interface.

Signed-off-by: Jerry Hoemann &lt;jerry.hoemann@hpe.com&gt;
[djbw: use command number constants instead of a magic mask value]
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;</content>
</entry>
<entry>
<title>libnvdimm, pmem: disable dax flushing when pmem is fronting a volatile region</title>
<updated>2017-06-29T16:29:50Z</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2017-06-09T16:46:50Z</published>
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<id>urn:sha1:0b277961f4484fb3f142caaa1dd1748cb0b2cbee</id>
<content type='text'>
The pmem driver attaches to both persistent and volatile memory ranges
advertised by the ACPI NFIT. When the region is volatile it is redundant
to spend cycles flushing caches at fsync(). Check if the hosting region
is volatile and do not set dax_write_cache() if it is.

Cc: Jan Kara &lt;jack@suse.cz&gt;
Cc: Jeff Moyer &lt;jmoyer@redhat.com&gt;
Cc: Christoph Hellwig &lt;hch@lst.de&gt;
Cc: Matthew Wilcox &lt;mawilcox@microsoft.com&gt;
Cc: Ross Zwisler &lt;ross.zwisler@linux.intel.com&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>x86, libnvdimm, pmem: remove global pmem api</title>
<updated>2017-06-27T23:29:54Z</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2017-01-14T04:36:58Z</published>
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<id>urn:sha1:ca6a4657e5420dec727256717e905ebc3c751352</id>
<content type='text'>
Now that all callers of the pmem api have been converted to dax helpers that
call back to the pmem driver, we can remove include/linux/pmem.h and
asm/pmem.h.

Cc: &lt;x86@kernel.org&gt;
Cc: Jeff Moyer &lt;jmoyer@redhat.com&gt;
Cc: Ingo Molnar &lt;mingo@redhat.com&gt;
Cc: Christoph Hellwig &lt;hch@lst.de&gt;
Cc: Toshi Kani &lt;toshi.kani@hpe.com&gt;
Cc: Oliver O'Halloran &lt;oohall@gmail.com&gt;
Cc: Ross Zwisler &lt;ross.zwisler@linux.intel.com&gt;
Reviewed-by: Jan Kara &lt;jack@suse.cz&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>libnvdimm, label: populate the type_guid property for v1.2 namespaces</title>
<updated>2017-06-15T21:31:40Z</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2017-06-06T18:10:51Z</published>
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<id>urn:sha1:faec6f8a1cd2c44e439de35ab3328c5cf7bf52d8</id>
<content type='text'>
The type_guid refers to the "Address Range Type GUID" for the region
backing a namespace as defined the ACPI NFIT (NVDIMM Firmware Interface
Table). This 'type' identifier specifies an access mechanism for the
given namespace. This capability replaces the confusing usage of the
'NSLABEL_FLAG_LOCAL' flag to indicate a block-aperture-mode namespace.

Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>libnvdimm, label: add v1.2 interleave-set-cookie algorithm</title>
<updated>2017-06-15T21:31:39Z</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2017-06-04T01:59:15Z</published>
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<id>urn:sha1:c12c48ce869d72029d70666f615cbd8f67fc14e9</id>
<content type='text'>
The interleave-set-cookie algorithm is extended to incorporate all the
same components that are used to generate an nvdimm unique-id. For
backwards compatibility we still maintain the old v1.1 definition.

Reported-by: Nicholas Moulin &lt;nicholas.w.moulin@intel.com&gt;
Reported-by: Kaushik Kanetkar &lt;kaushik.a.kanetkar@intel.com&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>libnvdimm: convert NDD_ flags to use bitops, introduce NDD_LOCKED</title>
<updated>2017-05-04T21:01:24Z</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2017-05-04T21:01:24Z</published>
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<id>urn:sha1:8f078b38dd382710884ce7abd31a1935c440e6f8</id>
<content type='text'>
This is a preparation patch for handling locked nvdimm label regions, a
new concept as introduced by the latest DSM document on pmem.io [1]. A
future patch will leverage nvdimm_set_locked() at DIMM probe time to
flag regions that can not be enabled. There should be no functional
difference resulting from this change.

[1]: http://pmem.io/documents/NVDIMM_DSM_Interface_Example-V1.3.pdf

Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>libnvdimm: rework region badblocks clearing</title>
<updated>2017-04-29T22:24:03Z</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2017-04-29T22:24:03Z</published>
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<id>urn:sha1:23f4984483623cf8621246004228f08fcabf51e4</id>
<content type='text'>
Toshi noticed that the new support for a region-level badblocks missed
the case where errors are cleared due to BTT I/O.

An initial attempt to fix this ran into a "sleeping while atomic"
warning due to taking the nvdimm_bus_lock() in the BTT I/O path to
satisfy the locking requirements of __nvdimm_bus_badblocks_clear().
However, that lock is not needed since we are not acting on any data that
is subject to change under that lock. The badblocks instance has its own
internal lock to handle mutations of the error list.

So, in order to make it clear that we are just acting on region devices,
rename __nvdimm_bus_badblocks_clear() to nvdimm_clear_badblocks_regions().
Eliminate the lock and consolidate all support routines for the new
nvdimm_account_cleared_poison() in drivers/nvdimm/bus.c. Finally, to the
opportunity to cleanup to some unnecessary casts, make the calling
convention of nvdimm_clear_badblocks_regions() clearer by replacing struct
resource with the minimal struct clear_badblocks_context, and use the
DEVICE_ATTR macro.

Cc: Dave Jiang &lt;dave.jiang@intel.com&gt;
Cc: Vishal Verma &lt;vishal.l.verma@intel.com&gt;
Reported-by: Toshi Kani &lt;toshi.kani@hpe.com&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
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