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<title>user/sven/linux.git/include/linux/libnvdimm.h, branch v4.19.274</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v4.19.274</id>
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<updated>2018-04-07T14:53:23Z</updated>
<entry>
<title>libnvdimm: Add of_node to region and bus descriptors</title>
<updated>2018-04-07T14:53:23Z</updated>
<author>
<name>Oliver O'Halloran</name>
<email>oohall@gmail.com</email>
</author>
<published>2018-04-06T05:21:13Z</published>
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<id>urn:sha1:1ff19f487a7e55bf3cebc96ea2a9a38d66fb7db7</id>
<content type='text'>
We want to be able to cross reference the region and bus devices
with the device tree node that they were spawned from. libNVDIMM
handles creating the actual devices for these internally, so we
need to pass in a pointer to the relevant node in the descriptor.

Signed-off-by: Oliver O'Halloran &lt;oohall@gmail.com&gt;
Acked-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
Acked-by: Balbir Singh &lt;bsingharora@gmail.com&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>libnvdimm: add an api to cast a 'struct nd_region' to its 'struct device'</title>
<updated>2018-04-03T18:51:42Z</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2018-04-02T20:14:25Z</published>
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<id>urn:sha1:243f29fe449bbead69076ad861dbe8f51b42c4d7</id>
<content type='text'>
For debug, it is useful for bus providers to be able to retrieve the
'struct device' associated with an nd_region instance that it
registered. We already have to_nd_region() to perform the reverse cast
operation, in fact its duplicate declaration can be removed from the
private drivers/nvdimm/nd.h header.

Reviewed-by: Dave Jiang &lt;dave.jiang@intel.com&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>acpi: nfit: add persistent memory control flag for nd_region</title>
<updated>2018-02-01T22:01:15Z</updated>
<author>
<name>Dave Jiang</name>
<email>dave.jiang@intel.com</email>
</author>
<published>2018-01-31T19:45:43Z</published>
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<id>urn:sha1:30e6d7bf29daa79d80711d35211c9b60894dbc44</id>
<content type='text'>
Propagate the ADR attribute flag from the NFIT platform capabilities
sub-table to nd_region.

Signed-off-by: Dave Jiang &lt;dave.jiang@intel.com&gt;
Reviewed-by: Ross Zwisler &lt;ross.zwisler@linux.intel.com&gt;
Signed-off-by: Ross Zwisler &lt;ross.zwisler@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>acpi: nfit: Add support for detect platform CPU cache flush on power loss</title>
<updated>2018-02-01T22:01:15Z</updated>
<author>
<name>Dave Jiang</name>
<email>dave.jiang@intel.com</email>
</author>
<published>2018-01-31T19:45:38Z</published>
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<id>urn:sha1:06e8ccdab15f46dfd31292e2b75d744bc5fc2a7c</id>
<content type='text'>
In ACPI 6.2a the platform capability structure has been added to the NFIT
tables. That provides software the ability to determine whether a system
supports the auto flushing of CPU caches on power loss. If the capability
is supported, we do not need to do dax_flush(). Plumbing the path to set the
property on per region from the NFIT tables.

This patch depends on the ACPI NFIT 6.2a platform capabilities support code
in include/acpi/actbl1.h.

Signed-off-by: Dave Jiang &lt;dave.jiang@intel.com&gt;
Reviewed-by: Ross Zwisler &lt;ross.zwisler@linux.intel.com&gt;
Signed-off-by: Ross Zwisler &lt;ross.zwisler@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>libnvdimm: move poison list functions to a new 'badrange' file</title>
<updated>2017-11-02T17:42:30Z</updated>
<author>
<name>Dave Jiang</name>
<email>dave.jiang@intel.com</email>
</author>
<published>2017-08-23T19:48:26Z</published>
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<id>urn:sha1:aa9ad44a42b4cf4387f8ecddaf8e51707fdcda5a</id>
<content type='text'>
nfit_test needs to use the poison list manipulation code as well. Make
it more generic and in the process rename poison to badrange, and move
all the related helpers to a new file.

Signed-off-by: Dave Jiang &lt;dave.jiang@intel.com&gt;
[vishal: Add badrange.o to nfit_test's Kbuild]
[vishal: add a missed include in bus.c for the new badrange functions]
[vishal: rename all instances of 'be' to 'bre']
Signed-off-by: Vishal Verma &lt;vishal.l.verma@intel.com&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>libnvdimm, nd_blk: remove mmio_flush_range()</title>
<updated>2017-08-31T22:05:10Z</updated>
<author>
<name>Robin Murphy</name>
<email>robin.murphy@arm.com</email>
</author>
<published>2017-08-31T11:27:09Z</published>
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<id>urn:sha1:5deb67f77a266010e2c10fb124b7516d0d258ce8</id>
<content type='text'>
mmio_flush_range() suffers from a lack of clearly-defined semantics,
and is somewhat ambiguous to port to other architectures where the
scope of the writeback implied by "flush" and ordering might matter,
but MMIO would tend to imply non-cacheable anyway. Per the rationale
in 67a3e8fe9015 ("nd_blk: change aperture mapping from WC to WB"), the
only existing use is actually to invalidate clean cache lines for
ARCH_MEMREMAP_PMEM type mappings *without* writeback. Since the recent
cleanup of the pmem API, that also now happens to be the exact purpose
of arch_invalidate_pmem(), which would be a far more well-defined tool
for the job.

Rather than risk potentially inconsistent implementations of
mmio_flush_range() for the sake of one callsite, streamline things by
removing it entirely and instead move the ARCH_MEMREMAP_PMEM related
definitions up to the libnvdimm level, so they can be shared by NFIT
as well. This allows NFIT to be enabled for arm64.

Signed-off-by: Robin Murphy &lt;robin.murphy@arm.com&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>nfit, libnvdimm, region: export 'position' in mapping info</title>
<updated>2017-08-05T00:20:16Z</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2017-08-05T00:20:16Z</published>
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<id>urn:sha1:401c0a19c6c22efcaff85d5a64a396f9130da2ca</id>
<content type='text'>
It is useful to be able to know the position of a DIMM in an
interleave-set. Consider the case where the order of the DIMMs changes
causing a namespace to be invalidated because the interleave-set cookie no
longer matches. If the before and after state of each DIMM position is
known this state debugged by the system owner.

Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'for-4.13/dax' into libnvdimm-for-next</title>
<updated>2017-07-03T23:54:58Z</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2017-07-03T23:54:58Z</published>
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<id>urn:sha1:9d92573fff3ec70785ef1815cc80573f70e7a921</id>
<content type='text'>
</content>
</entry>
<entry>
<title>libnvdimm, acpi, nfit: Add bus level dsm mask for pass thru.</title>
<updated>2017-07-01T15:49:59Z</updated>
<author>
<name>Jerry Hoemann</name>
<email>jerry.hoemann@hpe.com</email>
</author>
<published>2017-07-01T03:53:24Z</published>
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<id>urn:sha1:7db5bb33add5afe6c64e00516b0c928bfc937466</id>
<content type='text'>
Add a bus level dsm_mask to nvdimm_bus_descriptor to allow the passthru
calling mechanism to specify a different mask from the cmd_mask.

Populate bus_dsm_mask and use it to filter dsm calls that user can
make through the pass thru interface.

Signed-off-by: Jerry Hoemann &lt;jerry.hoemann@hpe.com&gt;
[djbw: use command number constants instead of a magic mask value]
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;</content>
</entry>
<entry>
<title>libnvdimm, pmem: disable dax flushing when pmem is fronting a volatile region</title>
<updated>2017-06-29T16:29:50Z</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2017-06-09T16:46:50Z</published>
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<id>urn:sha1:0b277961f4484fb3f142caaa1dd1748cb0b2cbee</id>
<content type='text'>
The pmem driver attaches to both persistent and volatile memory ranges
advertised by the ACPI NFIT. When the region is volatile it is redundant
to spend cycles flushing caches at fsync(). Check if the hosting region
is volatile and do not set dax_write_cache() if it is.

Cc: Jan Kara &lt;jack@suse.cz&gt;
Cc: Jeff Moyer &lt;jmoyer@redhat.com&gt;
Cc: Christoph Hellwig &lt;hch@lst.de&gt;
Cc: Matthew Wilcox &lt;mawilcox@microsoft.com&gt;
Cc: Ross Zwisler &lt;ross.zwisler@linux.intel.com&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
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