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<title>user/sven/linux.git/include/linux/mlx5/device.h, branch v4.9.46</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v4.9.46</id>
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<updated>2016-10-13T14:13:24Z</updated>
<entry>
<title>net/mlx5: Add MLX5_ARRAY_SET64 to fix BUILD_BUG_ON</title>
<updated>2016-10-13T14:13:24Z</updated>
<author>
<name>Tom Herbert</name>
<email>tom@herbertland.com</email>
</author>
<published>2016-10-12T01:57:10Z</published>
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<id>urn:sha1:b8a4ddb2e8f44f872fb93bbda2d541b27079fd2b</id>
<content type='text'>
I am hitting this in mlx5:

drivers/net/ethernet/mellanox/mlx5/core/pagealloc.c: In function
reclaim_pages_cmd.clone.0:
drivers/net/ethernet/mellanox/mlx5/core/pagealloc.c:346: error: call
to __compiletime_assert_346 declared with attribute error:
BUILD_BUG_ON failed: __mlx5_bit_off(manage_pages_out, pas[i]) % 64
drivers/net/ethernet/mellanox/mlx5/core/pagealloc.c: In function give_pages:
drivers/net/ethernet/mellanox/mlx5/core/pagealloc.c:291: error: call
to __compiletime_assert_291 declared with attribute error:
BUILD_BUG_ON failed: __mlx5_bit_off(manage_pages_in, pas[i]) % 64

Problem is that this is doing a BUILD_BUG_ON on a non-constant
expression because of trying to take offset of pas[i] in the
structure.

Fix is to create MLX5_ARRAY_SET64 that takes an additional argument
that is the field index to separate between BUILD_BUG_ON on the array
constant field and the indexed field to assign the value to.
There are two callers of MLX5_SET64 that are trying to get a variable
offset, change those to call MLX5_ARRAY_SET64 passing 'pas' and 'i'
as the arguments to use in the offset check and the indexed value
assignment.

Fixes: a533ed5e179cd ("net/mlx5: Pages management commands via mlx5 ifc")
Signed-off-by: Tom Herbert &lt;tom@herbertland.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Introduce sniffer steering hardware capabilities</title>
<updated>2016-08-18T15:49:59Z</updated>
<author>
<name>Maor Gottlieb</name>
<email>maorg@mellanox.com</email>
</author>
<published>2016-05-31T11:09:09Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=cea824d416522ce63d83b45fc0dc53c0f5b68cee'/>
<id>urn:sha1:cea824d416522ce63d83b45fc0dc53c0f5b68cee</id>
<content type='text'>
Define needed hardware capabilities for sniffer
RX and TX flow tables.

Add the following capabilities:
1. Sniffer RX flow table capabilities.
2. Sniffer TX flow table capabilities.
3. If same TIR can be used by multiple flow tables of different types.

Signed-off-by: Maor Gottlieb &lt;maorg@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Signed-off-by: Leon Romanovsky &lt;leon@kernel.org&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Unify and improve command interface</title>
<updated>2016-08-17T14:45:58Z</updated>
<author>
<name>Saeed Mahameed</name>
<email>saeedm@mellanox.com</email>
</author>
<published>2016-07-19T17:17:12Z</published>
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<id>urn:sha1:c4f287c4a6ac489c18afc4acc4353141a8c53070</id>
<content type='text'>
Now as all commands use mlx5 ifc interface, instead of doing two calls
for executing a command we embed command status checking into
mlx5_cmd_exec to simplify the interface.

Also we do here some cleanup for redundant software structures
(inbox/outbox) and functions and improved command failure output.

Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Signed-off-by: Leon Romanovsky &lt;leon@kernel.org&gt;
</content>
</entry>
<entry>
<title>{net,IB}/mlx5: MKey/PSV commands via mlx5 ifc</title>
<updated>2016-08-14T11:39:18Z</updated>
<author>
<name>Saeed Mahameed</name>
<email>saeedm@mellanox.com</email>
</author>
<published>2016-07-16T03:28:36Z</published>
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<id>urn:sha1:ec22eb53106be1472ba6573dc900943f52f8fd1e</id>
<content type='text'>
Remove old representation of manually created MKey/PSV commands layout,
and use mlx5_ifc canonical structures and defines.

Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Signed-off-by: Leon Romanovsky &lt;leon@kernel.org&gt;
</content>
</entry>
<entry>
<title>{net,IB}/mlx5: CQ commands via mlx5 ifc</title>
<updated>2016-08-14T11:39:15Z</updated>
<author>
<name>Saeed Mahameed</name>
<email>saeedm@mellanox.com</email>
</author>
<published>2016-07-15T23:33:22Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=278277866334e515141dde7c8ac143e15c0a767f'/>
<id>urn:sha1:278277866334e515141dde7c8ac143e15c0a767f</id>
<content type='text'>
Remove old representation of manually created CQ commands layout,
and use mlx5_ifc canonical structures and defines.

Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Signed-off-by: Leon Romanovsky &lt;leon@kernel.org&gt;
</content>
</entry>
<entry>
<title>net/mlx5: EQ commands via mlx5 ifc</title>
<updated>2016-08-14T11:39:12Z</updated>
<author>
<name>Saeed Mahameed</name>
<email>saeedm@mellanox.com</email>
</author>
<published>2016-07-16T00:26:15Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=73b626c182dff06867ceba996a819e8372c9b2ce'/>
<id>urn:sha1:73b626c182dff06867ceba996a819e8372c9b2ce</id>
<content type='text'>
Remove old representation of manually created EQ commands layout,
and use mlx5_ifc canonical structures and defines.

Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Signed-off-by: Leon Romanovsky &lt;leon@kernel.org&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Access register and MAD IFC commands via mlx5 ifc</title>
<updated>2016-08-14T11:38:57Z</updated>
<author>
<name>Saeed Mahameed</name>
<email>saeedm@mellanox.com</email>
</author>
<published>2016-07-16T21:46:41Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=20ed51c643b6296789a48adc3bc2cc875a1612cf'/>
<id>urn:sha1:20ed51c643b6296789a48adc3bc2cc875a1612cf</id>
<content type='text'>
Remove old representation of manually created ACCESS_REG/MAD_IFC
commands layout and use mlx5_ifc canonical structures and defines.

Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Signed-off-by: Leon Romanovsky &lt;leon@kernel.org&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Init/Teardown hca commands via mlx5 ifc</title>
<updated>2016-08-14T11:38:38Z</updated>
<author>
<name>Saeed Mahameed</name>
<email>saeedm@mellanox.com</email>
</author>
<published>2016-07-16T22:28:47Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=04ed5ad5db6880d53dd1bb8c93e82228a462a4dd'/>
<id>urn:sha1:04ed5ad5db6880d53dd1bb8c93e82228a462a4dd</id>
<content type='text'>
Remove old representation of manually created Init/Teardown hca
commands layout and use mlx5_ifc canonical structures and defines.

Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Signed-off-by: Leon Romanovsky &lt;leon@kernel.org&gt;
</content>
</entry>
<entry>
<title>net/mlx5e: Check the minimum inline header mode before xmit</title>
<updated>2016-07-26T00:53:40Z</updated>
<author>
<name>Hadar Hen Zion</name>
<email>hadarh@mellanox.com</email>
</author>
<published>2016-07-24T13:12:39Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=ae76715d153e33c249b6850361e4d8d775388b5a'/>
<id>urn:sha1:ae76715d153e33c249b6850361e4d8d775388b5a</id>
<content type='text'>
Each send queue (SQ) has inline mode that defines the minimal required
inline headers in the SQ WQE.
Before sending each packet check that the minimum required headers
on the WQE are copied.

Signed-off-by: Hadar Hen Zion &lt;hadarh@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Rate limit tables support</title>
<updated>2016-06-27T08:10:40Z</updated>
<author>
<name>Yevgeny Petrilin</name>
<email>yevgenyp@mellanox.com</email>
</author>
<published>2016-06-23T14:02:37Z</published>
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<id>urn:sha1:1466cc5b23d18e7b6b8f1a45443d595393dbcae7</id>
<content type='text'>
Configuring and managing HW rate limit tables.
The HW holds a table of rate limits, each rate is
associated with an index in that table.
Later a Send Queue uses this index to set the rate limit.
Multiple Send Queues can have the same rate limit, which is
represented by a single entry in this table.
Even though a rate can be shared, each queue is being rate
limited independently of others.

The SW shadow of this table holds the rate itself,
the index in the HW table and the refcount (number of queues)
working with this rate.

The exported functions are mlx5_rl_add_rate and mlx5_rl_remove_rate.
Number of different rates and their values are derived
from HW capabilities.

Signed-off-by: Yevgeny Petrilin &lt;yevgenyp@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
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