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<title>user/sven/linux.git/include/linux/mlx5/device.h, branch v5.15.26</title>
<subtitle>Linux Kernel
</subtitle>
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<updated>2021-08-11T18:14:33Z</updated>
<entry>
<title>net/mlx5: Allocate individual capability</title>
<updated>2021-08-11T18:14:33Z</updated>
<author>
<name>Parav Pandit</name>
<email>parav@nvidia.com</email>
</author>
<published>2021-07-13T11:17:03Z</published>
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<id>urn:sha1:48f02eef7f764f33e520ed8009d293396ca690cd</id>
<content type='text'>
Currently mlx5_core_dev contains array of capabilities. It contains 19
valid capabilities of the device, 2 reserved entries and 12 holes.
Due to this for 14 unused entries, mlx5_core_dev allocates 14 * 8K = 112K
bytes of memory which is never used. Due to this mlx5_core_dev structure
size is 270Kbytes odd. This allocation further aligns to next power of 2
to 512Kbytes.

By skipping non-existent entries,
(a) 112Kbyte is saved,
(b) mlx5_core_dev reduces to 8KB with alignment
(c) 350KB saved in alignment

In future individual capability allocation can be used to skip its
allocation when such capability is disabled at the device level. This
patch prepares mlx5_core_dev to hold capability using a pointer instead
of inline array.

Signed-off-by: Parav Pandit &lt;parav@nvidia.com&gt;
Reviewed-by: Leon Romanovsky &lt;leonro@nvidia.com&gt;
Reviewed-by: Shay Drory &lt;shayd@nvidia.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@nvidia.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Reorganize current and maximal capabilities to be per-type</title>
<updated>2021-08-11T18:14:32Z</updated>
<author>
<name>Parav Pandit</name>
<email>parav@nvidia.com</email>
</author>
<published>2021-07-13T09:36:05Z</published>
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<id>urn:sha1:5958a6fad623ad3b67a9e4d8dbd5f1874cc7039e</id>
<content type='text'>
In the current code, the current and maximal capabilities are
maintained in separate arrays which are both per type. In order to
allow the creation of such a basic structure as a dynamically
allocated array, we move curr and max fields to a unified
structure so that specific capabilities can be allocated as one unit.

Signed-off-by: Parav Pandit &lt;parav@nvidia.com&gt;
Reviewed-by: Leon Romanovsky &lt;leonro@nvidia.com&gt;
Reviewed-by: Shay Drory &lt;shayd@nvidia.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@nvidia.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Fix typo in comments</title>
<updated>2021-08-11T18:14:30Z</updated>
<author>
<name>Cai Huoqing</name>
<email>caihuoqing@baidu.com</email>
</author>
<published>2021-07-30T03:03:00Z</published>
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<id>urn:sha1:39c538d64479c949aaeca4fe73d2226f715adfb7</id>
<content type='text'>
Fix typo:
*vectores  ==&gt; vectors
*realeased  ==&gt; released
*erros  ==&gt; errors
*namepsace  ==&gt; namespace
*trafic  ==&gt; traffic
*proccessed  ==&gt; processed
*retore  ==&gt; restore
*Currenlty  ==&gt; Currently
*crated  ==&gt; created
*chane  ==&gt; change
*cannnot  ==&gt; cannot
*usuallly  ==&gt; usually
*failes  ==&gt; fails
*importent  ==&gt; important
*reenabled  ==&gt; re-enabled
*alocation  ==&gt; allocation
*recived  ==&gt; received
*tanslation  ==&gt; translation

Signed-off-by: Cai Huoqing &lt;caihuoqing@baidu.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@nvidia.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: mlx5_ifc support for header insert/remove</title>
<updated>2021-06-10T01:36:06Z</updated>
<author>
<name>Yevgeny Kliteynik</name>
<email>kliteyn@nvidia.com</email>
</author>
<published>2021-03-09T01:29:16Z</published>
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<id>urn:sha1:67133eaa93e810f5c510cd0ec6e2e7ca76fc1340</id>
<content type='text'>
Add support for HCA caps 2 that contains capabilities for the new
insert/remove header actions.

Added the required definitions for supporting the new reformat type:
added packet reformat parameters, reformat anchors and definitions
to allow copy/set into the inserted EMD (Embedded MetaData) tag.

Signed-off-by: Yevgeny Kliteynik &lt;kliteyn@nvidia.com&gt;
Signed-off-by: Vlad Buslov &lt;vladbu@nvidia.com&gt;
Reviewed-by: Jianbo Liu &lt;jianbol@nvidia.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@nvidia.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5e: RX, Add checks for calculated Striding RQ attributes</title>
<updated>2021-04-20T03:17:09Z</updated>
<author>
<name>Tariq Toukan</name>
<email>tariqt@nvidia.com</email>
</author>
<published>2020-06-21T18:35:34Z</published>
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<id>urn:sha1:6980ffa0c5a8e65d53ff803d2cafdba3e2022714</id>
<content type='text'>
Striding RQ attributes below are mutually dependent. An unaware
change to one might take the others out of the valid range derived
by the HW caps:
- The MPWQE size in bytes
- The number of strides in a MPWQE
- The stride size

Add checks to verify they are valid and comply to the HW spec
and SW assumptions/requirements.
This is not a fix, no particular issue exists today.

Signed-off-by: Tariq Toukan &lt;tariqt@nvidia.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@nvidia.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5e: Allow to match on ICMP parameters</title>
<updated>2021-03-12T23:29:34Z</updated>
<author>
<name>Maor Dickman</name>
<email>maord@nvidia.com</email>
</author>
<published>2021-01-24T13:56:36Z</published>
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<id>urn:sha1:a3222a2da0a2d6c7682252d4bfdff05721a82b95</id>
<content type='text'>
Support matching on ICMPv4/6 type and code parameters using misc3
section of match parameters.

Signed-off-by: Maor Dickman &lt;maord@nvidia.com&gt;
Reviewed-by: Roi Dayan &lt;roid@nvidia.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@nvidia.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux</title>
<updated>2021-02-16T22:53:30Z</updated>
<author>
<name>David S. Miller</name>
<email>davem@davemloft.net</email>
</author>
<published>2021-02-16T22:53:30Z</published>
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<id>urn:sha1:44c32039751ad1506b188a8ffa8f1a7b9726d29e</id>
<content type='text'>
Saeed Mahameed says:
====================
pull-request: mlx5-next 2021-02-16

The patches in this pr are already submitted and reviewed through the
netdev and rdma mailing lists.

The series includes mlx5 HW bits and definitions for mlx5 real time clock
translation and handling in the mlx5 driver clock module to enable and
support such mode [1]

[1] https://patchwork.kernel.org/project/netdevbpf/patch/20210212223042.449816-7-saeed@kernel.org/
====================

Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Add register layout to support real-time time-stamp</title>
<updated>2021-02-16T22:04:54Z</updated>
<author>
<name>Eran Ben Elisha</name>
<email>eranbe@mellanox.com</email>
</author>
<published>2021-02-12T22:30:38Z</published>
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<id>urn:sha1:ae02d41551d6f2a035d3e63ce4415e1b2ba3a7e6</id>
<content type='text'>
Add needed structure layouts and defines for MTUTC (Management UTC)
register. MTUTC will be used for cyc2time HW translation.

In addition, add cyc2time modify capability bit and init segment HCA
real time address.

Finally, add capability bits indicating which time-stamping format is
supported per SQ and RQ. Add ts_format in the queue's context layout to
allow configuration.

Signed-off-by: Eran Ben Elisha &lt;eranbe@mellanox.com&gt;
Signed-off-by: Aya Levin &lt;ayal@nvidia.com&gt;
Reviewed-by: Moshe Shemesh &lt;moshe@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@nvidia.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5e: Add trap entity to ETH driver</title>
<updated>2021-01-28T03:53:53Z</updated>
<author>
<name>Aya Levin</name>
<email>ayal@nvidia.com</email>
</author>
<published>2021-01-26T23:24:16Z</published>
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<id>urn:sha1:5543e989fe5e2fe6a5829ee42c00152cac2bb8a0</id>
<content type='text'>
Introduce mlx5e_trap which includes a dedicated RQ and NAPI for trapped
packets. Trap-RQ processes packets that were destined to be dropped,
but for debug and visibility sake these packets are trapped and reported
to devlink.
Trap-RQ connects between the HW and the driver and is not a part of a
channel. Open mlx5e_create_rq() and mlx5_core_destroy_rq() as API and
add dedicate RQ handlers which report to devlink of trapped packets.

Signed-off-by: Aya Levin &lt;ayal@nvidia.com&gt;
Reviewed-by: Tariq Toukan &lt;tariqt@nvidia.com&gt;
Signed-off-by: Tariq Toukan &lt;tariqt@nvidia.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@nvidia.com&gt;
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Notify on trap action by blocking event</title>
<updated>2021-01-28T03:53:51Z</updated>
<author>
<name>Aya Levin</name>
<email>ayal@nvidia.com</email>
</author>
<published>2021-01-26T23:24:11Z</published>
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<id>urn:sha1:241dc159391fb9d351362d911a39dff84074cc92</id>
<content type='text'>
In order to allow mlx5 core driver to trigger synchronous operations to
its consumers, add a blocking events handler. Add wrappers to
blocking_notifier_[call_chain/chain_register/chain_unregister]. Add trap
callback for action set and notify about this change. Following patches
in the set add a listener for this event.

Signed-off-by: Aya Levin &lt;ayal@nvidia.com&gt;
Reviewed-by: Tariq Toukan &lt;tariqt@nvidia.com&gt;
Signed-off-by: Tariq Toukan &lt;tariqt@nvidia.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@nvidia.com&gt;
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
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