<feed xmlns='http://www.w3.org/2005/Atom'>
<title>user/sven/linux.git/include/linux/mlx5/device.h, branch v5.3.14</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v5.3.14</id>
<link rel='self' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v5.3.14'/>
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<updated>2019-08-08T20:01:19Z</updated>
<entry>
<title>net/mlx5: kTLS, Fix wrong TIS opmod constants</title>
<updated>2019-08-08T20:01:19Z</updated>
<author>
<name>Tariq Toukan</name>
<email>tariqt@mellanox.com</email>
</author>
<published>2019-07-21T11:18:42Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=26149e3e1f44d27897d0af9ca4bcd723674bad44'/>
<id>urn:sha1:26149e3e1f44d27897d0af9ca4bcd723674bad44</id>
<content type='text'>
Fix the used constants for TLS TIS opmods, per the HW specification.

Fixes: a12ff35e0fb7 ("net/mlx5: Introduce TLS TX offload hardware bits and structures")
Signed-off-by: Tariq Toukan &lt;tariqt@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux</title>
<updated>2019-07-04T20:42:59Z</updated>
<author>
<name>Saeed Mahameed</name>
<email>saeedm@mellanox.com</email>
</author>
<published>2019-07-04T20:40:32Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=e08a976a16cafc20931db1d17aed9183202bfa8d'/>
<id>urn:sha1:e08a976a16cafc20931db1d17aed9183202bfa8d</id>
<content type='text'>
Misc updates from mlx5-next branch:

1) Add the required HW definitions and structures for upcoming TLS
   support.
2) Add support for MCQI and MCQS hardware registers for fw version query.
3) Added hardware bits and structures definitions for sub-functions
4) Small code cleanup and improvement for PF pci driver.
5) Bluefield (ECPF) updates and refactoring for better E-Switch
   management on ECPF embedded CPU NIC:
   5.1) Consolidate querying eswitch number of VFs
   5.2) Register event handler at the correct E-Switch init stage
   5.3) Setup PF's inline mode and vlan pop when the ECPF is the
        E-Swtich manager ( the host PF is basically a VF ).
   5.4) Handle Vport UC address changes in switchdev mode.

6) Cleanup the rep and netdev reference when unloading IB rep.

Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;

i# All conflicts fixed but you are still merging.
</content>
</entry>
<entry>
<title>net/mlx5: Introduce TLS TX offload hardware bits and structures</title>
<updated>2019-07-03T19:50:42Z</updated>
<author>
<name>Eran Ben Elisha</name>
<email>eranbe@mellanox.com</email>
</author>
<published>2019-04-03T10:05:50Z</published>
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<id>urn:sha1:a12ff35e0fb770b4d060298be147189313ec002c</id>
<content type='text'>
Add TLS offload related IFC structs, layouts and enumerations.

Signed-off-by: Eran Ben Elisha &lt;eranbe@mellanox.com&gt;
Signed-off-by: Tariq Toukan &lt;tariqt@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Use event mask based on device capabilities</title>
<updated>2019-07-03T17:55:45Z</updated>
<author>
<name>Yishai Hadas</name>
<email>yishaih@mellanox.com</email>
</author>
<published>2019-06-30T16:23:23Z</published>
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<id>urn:sha1:b9a7ba5562074855e8a3f92ea7e1174b61a3e87d</id>
<content type='text'>
Use the reported device capabilities for the supported user events (i.e.
affiliated and un-affiliated) to set the EQ mask.

As the event mask can be up to 256 defined by 4 entries of u64 change
the applicable code to work accordingly.

Signed-off-by: Yishai Hadas &lt;yishaih@mellanox.com&gt;
Acked-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Issue SW reset on FW assert</title>
<updated>2019-06-13T20:23:18Z</updated>
<author>
<name>Feras Daoud</name>
<email>ferasda@mellanox.com</email>
</author>
<published>2018-11-12T14:40:17Z</published>
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<id>urn:sha1:3e5b72ac2f298423902169db7893fef43365e0a6</id>
<content type='text'>
If a FW assert is considered fatal, indicated by a new bit in the health
buffer, reset the FW. After the reset go through the normal recovery
flow. Only one PF needs to issue the reset, so an attempt is made to
prevent the 2nd function from also issuing the reset.
It's not an error if that happens, it just slows recovery.

Signed-off-by: Feras Daoud &lt;ferasda@mellanox.com&gt;
Signed-off-by: Alex Vesker &lt;valex@mellanox.com&gt;
Signed-off-by: Moshe Shemesh &lt;moshe@mellanox.com&gt;
Signed-off-by: Daniel Jurgens &lt;danielj@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: E-Switch, Replace host_params event with functions_changed event</title>
<updated>2019-05-31T19:28:14Z</updated>
<author>
<name>Vu Pham</name>
<email>vuhuong@mellanox.com</email>
</author>
<published>2019-05-29T22:50:34Z</published>
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<id>urn:sha1:cd56f929e6a547180f889a4def370bdd6d48d223</id>
<content type='text'>
To support sriov on a E-Switch manager, num_vfs are queried
to the firmware whenever E-Switch manager is notified by
esw_functions_changed event.

Replace host_params event with esw_functions_changed event that reflects
more appropriate naming.

While at it, also correct num_vfs type from int to u16 as expected by
the function mlx5_esw_query_functions().

Signed-off-by: Vu Pham &lt;vuhuong@mellanox.com&gt;
Reviewed-by: Parav Pandit &lt;parav@mellanox.com&gt;
Reviewed-by: Bodong Wang &lt;bodong@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux</title>
<updated>2019-05-01T20:57:48Z</updated>
<author>
<name>Saeed Mahameed</name>
<email>saeedm@mellanox.com</email>
</author>
<published>2019-05-01T20:57:17Z</published>
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<id>urn:sha1:c515e70d675421240ff6628a1831a56e4ea0e82c</id>
<content type='text'>
This merge commit includes some misc shared code updates from mlx5-next branch needed
for net-next.

1) From Aya: Enable general events on all physical link types and
   restrict general event handling of subtype DELAY_DROP_TIMEOUT in mlx5 rdma
   driver to ethernet links only as it was intended.

2) From Eli: Introduce low level bits for prio tag mode

3) From Maor: Low level steering updates to support RDMA RX flow
   steering and enables RoCE loopback traffic when switchdev is enabled.

4) From Vu and Parav: Two small mlx5 core cleanups

5) From Yevgeny add HW definitions of geneve offloads

Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Geneve, Add flow table capabilities for Geneve decap with TLV options</title>
<updated>2019-04-29T23:55:38Z</updated>
<author>
<name>Yevgeny Kliteynik</name>
<email>kliteyn@mellanox.com</email>
</author>
<published>2019-04-29T18:14:20Z</published>
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<id>urn:sha1:b169e64a24442e02cafee1586f17fcb713fe65a6</id>
<content type='text'>
Introduce specification for Geneve decap flow with encapsulation options
and allow creation of rules that are matching on Geneve TLV options.

Reviewed-by: Oz Shlomo &lt;ozsh@mellanox.com&gt;
Signed-off-by: Yevgeny Kliteynik &lt;kliteyn@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Add support in RDMA RX steering</title>
<updated>2019-04-29T23:55:05Z</updated>
<author>
<name>Maor Gottlieb</name>
<email>maorg@mellanox.com</email>
</author>
<published>2019-04-29T18:14:12Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=d83eb50e29de36ddc819863ab7b9d2da58bccbd0'/>
<id>urn:sha1:d83eb50e29de36ddc819863ab7b9d2da58bccbd0</id>
<content type='text'>
Add new flow steering namespace - MLX5_FLOW_NAMESPACE_RDMA_RX.
Flow steering rules in this namespace are used to filter
RDMA traffic.

Signed-off-by: Maor Gottlieb &lt;maorg@mellanox.com&gt;
Reviewed-by: Mark Bloch &lt;markb@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Handle event of power detection in the PCIE slot</title>
<updated>2019-04-05T21:10:32Z</updated>
<author>
<name>Aya Levin</name>
<email>ayal@mellanox.com</email>
</author>
<published>2019-03-24T07:21:40Z</published>
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<id>urn:sha1:5d3c537f907036c1f18bd325ffc356e24cde664c</id>
<content type='text'>
Handle event of power state change in the PCIE slot. When the event
occurs, check if query power state and PCI power fields is supported. If
so, read these fields from MPEIN (management PCIE info) register and
issue a corresponding message.

Signed-off-by: Aya Levin &lt;ayal@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
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