<feed xmlns='http://www.w3.org/2005/Atom'>
<title>user/sven/linux.git/include/linux/mlx5/driver.h, branch v4.10.3</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v4.10.3</id>
<link rel='self' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v4.10.3'/>
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<updated>2016-12-28T19:36:52Z</updated>
<entry>
<title>Revert "net/mlx5: Add MPCNT register infrastructure"</title>
<updated>2016-12-28T19:36:52Z</updated>
<author>
<name>Gal Pressman</name>
<email>galp@mellanox.com</email>
</author>
<published>2016-12-28T12:58:39Z</published>
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<id>urn:sha1:1efbd205b3cc5882a8c386c58a57134044e9d5ba</id>
<content type='text'>
This reverts commit 7f503169cabd70c1f13b9279c50eca7dfb9a7d51.

Fixes: 7f503169cabd ("net/mlx5: Add MPCNT register infrastructure")
Signed-off-by: Gal Pressman &lt;galp@mellanox.com&gt;
Reported-by: Jesper Dangaard Brouer &lt;brouer@redhat.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net/mlx5e: Implement Fragmented Work Queue (WQ)</title>
<updated>2016-12-02T15:47:01Z</updated>
<author>
<name>Tariq Toukan</name>
<email>tariqt@mellanox.com</email>
</author>
<published>2016-11-30T15:59:37Z</published>
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<id>urn:sha1:1c1b522808a18402f043c1418b4e48c7355480cc</id>
<content type='text'>
Add new type of struct mlx5_frag_buf which is used to allocate fragmented
buffers rather than contiguous, and make the Completion Queues (CQs) use
it as they are big (default of 2MB per CQ in Striding RQ).

This fixes the failures of type:
"mlx5e_open_locked: mlx5e_open_channels failed, -12"
due to dma_zalloc_coherent insufficient contiguous coherent memory to
satisfy the driver's request when the user tries to setup more or larger
rings.

Signed-off-by: Tariq Toukan &lt;tariqt@mellanox.com&gt;
Reported-by: Sebastian Ott &lt;sebott@linux.vnet.ibm.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Add DCBX firmware commands support</title>
<updated>2016-11-28T20:09:35Z</updated>
<author>
<name>Huy Nguyen</name>
<email>huyn@mellanox.com</email>
</author>
<published>2016-11-27T15:02:06Z</published>
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<id>urn:sha1:341c5ee2fb78420ffc441df36f93226be8069b0a</id>
<content type='text'>
Add set/query commands for DCBX_PARAM register

Signed-off-by: Huy Nguyen &lt;huyn@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Add MPCNT register infrastructure</title>
<updated>2016-11-18T17:08:58Z</updated>
<author>
<name>Gal Pressman</name>
<email>galp@mellanox.com</email>
</author>
<published>2016-11-17T11:46:01Z</published>
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<id>urn:sha1:7f503169cabd70c1f13b9279c50eca7dfb9a7d51</id>
<content type='text'>
Add the needed infrastructure for future use of MPCNT register.

Signed-off-by: Gal Pressman &lt;galp@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Add handling for port module event</title>
<updated>2016-11-18T17:08:57Z</updated>
<author>
<name>Huy Nguyen</name>
<email>huyn@mellanox.com</email>
</author>
<published>2016-11-17T11:45:57Z</published>
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<id>urn:sha1:d4eb4cd78b0774c7061db56844ed2ea7790cc77c</id>
<content type='text'>
For each asynchronous port module event:
  1. print with ratelimit to the dmesg log
  2. increment the corresponding event counter

Signed-off-by: Huy Nguyen &lt;huyn@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Make the command interface cache more flexible</title>
<updated>2016-11-18T17:08:56Z</updated>
<author>
<name>Mohamad Haj Yahia</name>
<email>mohamad@mellanox.com</email>
</author>
<published>2016-11-17T11:45:55Z</published>
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<id>urn:sha1:0ac3ea70897fb9f84b620aeda074ecccf481629d</id>
<content type='text'>
Add more cache command size sets and more entries for each set based on
the current commands set different sizes and commands frequency.

Fixes: e126ba97dba9 ('mlx5: Add driver for Mellanox Connect-IB adapters')
Signed-off-by: Mohamad Haj Yahia &lt;mohamad@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net/mlx5: PCI error recovery health care simulation</title>
<updated>2016-10-29T16:00:39Z</updated>
<author>
<name>Mohamad Haj Yahia</name>
<email>mohamad@mellanox.com</email>
</author>
<published>2016-10-25T15:36:34Z</published>
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<id>urn:sha1:04c0c1ab38e95105d950db5b84e727637e149ce7</id>
<content type='text'>
In case that the kernel PCI error handlers are not called, we will
trigger our own recovery flow.

The health work will give priority to the kernel pci error handlers to
recover the PCI by waiting for a small period, if the pci error handlers
are not triggered the manual recovery flow will be executed.

We don't save pci state in case of manual recovery because it will ruin the
pci configuration space and we will lose dma sync.

Fixes: 89d44f0a6c73 ('net/mlx5_core: Add pci error handlers to mlx5_core driver')
Signed-off-by: Mohamad Haj Yahia &lt;mohamad@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Fix race between PCI error handlers and health work</title>
<updated>2016-10-29T16:00:39Z</updated>
<author>
<name>Mohamad Haj Yahia</name>
<email>mohamad@mellanox.com</email>
</author>
<published>2016-10-25T15:36:33Z</published>
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<id>urn:sha1:05ac2c0b7438ea08c5d54b48797acf9b22cb2f6f</id>
<content type='text'>
Currently there is a race between the health care work and the kernel
pci error handlers because both of them detect the error, the first one
to be called will do the error handling.
There is a chance that health care will disable the pci after resuming
pci slot.
Also create a separate WQ because now we will have two types of health
works, one for the error detection and one for the recovery.

Fixes: 89d44f0a6c73 ('net/mlx5_core: Add pci error handlers to mlx5_core driver')
Signed-off-by: Mohamad Haj Yahia &lt;mohamad@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>{net, ib}/mlx5: Make cache line size determination at runtime.</title>
<updated>2016-10-29T16:00:39Z</updated>
<author>
<name>Daniel Jurgens</name>
<email>danielj@mellanox.com</email>
</author>
<published>2016-10-25T15:36:24Z</published>
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<id>urn:sha1:b47bd6ea40636362a8b6605de51207cc387ba0b8</id>
<content type='text'>
ARM 64B cache line systems have L1_CACHE_BYTES set to 128.
cache_line_size() will return the correct size.

Fixes: cf50b5efa2fe('net/mlx5_core/ib: New device capabilities
handling.')
Signed-off-by: Daniel Jurgens &lt;danielj@mellanox.com&gt;

Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Introduce attach/detach to interface API</title>
<updated>2016-09-11T04:21:49Z</updated>
<author>
<name>Mohamad Haj Yahia</name>
<email>mohamad@mellanox.com</email>
</author>
<published>2016-09-09T14:35:19Z</published>
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<id>urn:sha1:737a234bb6384800a5b632be85c6b0ad6221d137</id>
<content type='text'>
Add attach/detach callbacks to interface API.
This is crucial for implementing seamless reset flow which releases the
hardware and it's resources upon detach while keeping software
structures and state (e.g netdev) then reset and reallocate the hardware
needed resources upon attach.

Signed-off-by: Mohamad Haj Yahia &lt;mohamad@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
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