Linux Kernel https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v5.16.19 2021-10-28T04:33:28Z 2021-10-28T04:33:28Z Saeed Mahameed saeedm@nvidia.com 2021-10-27T19:45:37Z urn:sha1:573bce9e675b0654e18a338ca9a64187fc19806f Signed-off-by: Saeed Mahameed <saeedm@nvidia.com> 2021-10-26T17:18:32Z Jakub Kicinski kuba@kernel.org 2021-10-26T15:29:39Z urn:sha1:6b3671746a8a3aa05316b829e1357060f35009c1 revert commit 46ae40b94d88 ("net/mlx5: Let user configure io_eq_size param") revert commit a6cb08daa3b4 ("net/mlx5: Let user configure event_eq_size param") revert commit 554604061979 ("net/mlx5: Let user configure max_macs param") The EQE parameters are applicable to more drivers, they should be configured via standard API, probably ethtool. Example of another driver needing something similar: https://lore.kernel.org/all/1633454136-14679-3-git-send-email-sbhatta@marvell.com/ The last param for "max_macs" is probably fine but the documentation is severely lacking. The meaning and implications for changing the param need to be stated. Link: https://lore.kernel.org/r/20211026152939.3125950-1-kuba@kernel.org Signed-off-by: Jakub Kicinski <kuba@kernel.org> 2021-10-25T20:51:20Z Shay Drory shayd@nvidia.com 2021-08-12T08:53:34Z urn:sha1:46ae40b94d8826591472798114a723cc7feac7a7 Currently, each I/O EQ is taking 128KB of memory. This size is not needed in all use cases, and is critical with large scale. Hence, allow user to configure the size of I/O EQs. For example, to reduce I/O EQ size to 64, execute: $ devlink resource set pci/0000:00:0b.0 path /io_eq_size/ size 64 $ devlink dev reload pci/0000:00:0b.0 Signed-off-by: Shay Drory <shayd@nvidia.com> Reviewed-by: Moshe Shemesh <moshe@nvidia.com> Reviewed-by: Parav Pandit <parav@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com> 2021-10-25T20:51:19Z Aya Levin ayal@nvidia.com 2021-10-13T06:45:22Z urn:sha1:5a1023deeed02a2078bcc11eec1c4be31e85892d Firmware logs its asserts also to non-volatile memory. In order to reduce drift between the NIC and the host, the driver sets the host epoch-time to the firmware every hour. Signed-off-by: Aya Levin <ayal@nvidia.com> Reviewed-by: Moshe Shemesh <moshe@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com> 2021-10-22T10:41:16Z David S. Miller davem@davemloft.net 2021-10-22T10:41:16Z urn:sha1:bdfa75ad70e93633e18b1ed2b3866c01aa9bf9d2 Lots of simnple overlapping additions. With a build fix from Stephen Rothwell. Signed-off-by: David S. Miller <davem@davemloft.net> 2021-10-21T05:27:39Z Leon Romanovsky leonro@nvidia.com 2021-10-21T05:27:39Z urn:sha1:60dd57c7479418e2bc902143eb46a2fdcfeecbbb A small series to clean up the mlx5 mkey code across the mlx5_core and InfiniBand. * branch 'mlx5_mkey': RDMA/mlx5: Attach ndescs to mlx5_ib_mkey RDMA/mlx5: Move struct mlx5_core_mkey to mlx5_ib RDMA/mlx5: Replace struct mlx5_core_mkey by u32 key RDMA/mlx5: Remove pd from struct mlx5_core_mkey RDMA/mlx5: Remove size from struct mlx5_core_mkey RDMA/mlx5: Remove iova from struct mlx5_core_mkey Signed-off-by: Leon Romanovsky <leonro@nvidia.com> 2021-10-20T17:42:49Z Maor Dickman maord@nvidia.com 2021-10-07T13:05:38Z urn:sha1:14fe2471c62816ba82546fb68369d957c3a58b59 Both multipath and bonding events are changing the HW LAG state independently. Handling one of the features events while the other is already enabled can cause unwanted behavior, for example handling bonding event while multipath enabled will disable the lag and cause multipath to stop working. Fix it by ignoring bonding event while in multipath and ignoring FIB events while in bonding mode. Fixes: 544fe7c2e654 ("net/mlx5e: Activate HW multipath and handle port affinity based on FIB events") Signed-off-by: Maor Dickman <maord@nvidia.com> Reviewed-by: Roi Dayan <roid@nvidia.com> Reviewed-by: Mark Bloch <mbloch@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com> 2021-10-19T11:35:28Z Aharon Landau aharonl@nvidia.com 2021-10-12T10:26:34Z urn:sha1:4123bfb0b28b77b944360be8c758b1a0974e96ad Move mlx5_core_mkey struct to mlx5_ib, as the mlx5_core doesn't use it at this point. Signed-off-by: Aharon Landau <aharonl@nvidia.com> Reviewed-by: Shay Drory <shayd@nvidia.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Leon Romanovsky <leonro@nvidia.com> 2021-10-19T11:34:12Z Aharon Landau aharonl@nvidia.com 2021-10-12T10:26:33Z urn:sha1:83fec3f12a5904b62330fd1a89af6d892afc387e In mlx5_core and vdpa there is no use of mlx5_core_mkey members except for the key itself. As preparation for moving mlx5_core_mkey to mlx5_ib, the occurrences of struct mlx5_core_mkey in all modules except for mlx5_ib are replaced by a u32 key. Signed-off-by: Aharon Landau <aharonl@nvidia.com> Reviewed-by: Shay Drory <shayd@nvidia.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Leon Romanovsky <leonro@nvidia.com> 2021-10-19T11:33:58Z Aharon Landau aharonl@nvidia.com 2021-10-12T10:26:32Z urn:sha1:c64674168b6a2f293e92caf33c917ccf10886801 There is no read of mkey->pd, only write. Remove it. Signed-off-by: Aharon Landau <aharonl@nvidia.com> Reviewed-by: Shay Drory <shayd@nvidia.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Leon Romanovsky <leonro@nvidia.com>