<feed xmlns='http://www.w3.org/2005/Atom'>
<title>user/sven/linux.git/include/linux/mlx5/qp.h, branch v6.3.12</title>
<subtitle>Linux Kernel
</subtitle>
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<updated>2023-02-17T20:22:22Z</updated>
<entry>
<title>net/mlx5: Change define name for 0x100 lkey value</title>
<updated>2023-02-17T20:22:22Z</updated>
<author>
<name>Or Har-Toov</name>
<email>ohartoov@nvidia.com</email>
</author>
<published>2023-01-17T13:14:50Z</published>
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<id>urn:sha1:a419bfb7632095410adc3aecb1e863568f049add</id>
<content type='text'>
Change define of 0x100 lkey value from MLX5_INVALID_LKEY to be
MLX5_TERMINATE_SCATTER_LIST_LKEY as 0x100 is the value of
terminate_scatter_list_mkey.

Link: https://lore.kernel.org/r/3a116dc3fbae4cb6b76a63d27d418830b06ade0c.1673960981.git.leon@kernel.org
Signed-off-by: Or Har-Toov &lt;ohartoov@nvidia.com&gt;
Reviewed-by: Michael Guralnik &lt;michaelgur@nvidia.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@nvidia.com&gt;
Signed-off-by: Jason Gunthorpe &lt;jgg@nvidia.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5e: xsk: Use KSM for unaligned XSK</title>
<updated>2022-09-30T14:55:46Z</updated>
<author>
<name>Maxim Mikityanskiy</name>
<email>maximmi@nvidia.com</email>
</author>
<published>2022-09-29T07:21:46Z</published>
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<id>urn:sha1:6470d2e7e8ed8e9dd560d8dc3e09d1100a17ee26</id>
<content type='text'>
UMR MTTs used in striding RQ have certain alignment requirements. While
it's guaranteed to work when UMR pages are aligned to the UMR page size,
in practice it works then UMR pages are aligned to 8 bytes. However,
it's still not enough flexibility for the unaligned mode of XSK. This
patch leverages KSM to map UMR pages without alignment requirements,
when unaligned XSK is active. The downside is that KSM entries are twice
as big as MTTs, which limits the maximum WQE size, so regular RQs and
aligned XSK continue using MTTs.

Signed-off-by: Maxim Mikityanskiy &lt;maximmi@nvidia.com&gt;
Reviewed-by: Tariq Toukan &lt;tariqt@nvidia.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@nvidia.com&gt;
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>net/mlx5e: Use runtime page_shift for striding RQ</title>
<updated>2022-09-30T14:55:45Z</updated>
<author>
<name>Maxim Mikityanskiy</name>
<email>maximmi@nvidia.com</email>
</author>
<published>2022-09-29T07:21:42Z</published>
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<id>urn:sha1:e5a3cc83d54019a90119ce0cf17b5e21729b79bf</id>
<content type='text'>
This commit allows striding RQ to determine MTT page size at runtime,
instead of sticking to the compile-time PAGE_SIZE. This functionality
will be used by a following commit that adjusts the MTT page size to the
XSK frame size.

Stick with PAGE_SIZE for XSK on legacy RQ, as frag_stride is not used in
data path, it only helps calculate how pages are partitioned into
fragments, and PAGE_SIZE will ensure each fragment starts at the
beginning of a new allocation unit (XSK frame).

Signed-off-by: Maxim Mikityanskiy &lt;maximmi@nvidia.com&gt;
Reviewed-by: Tariq Toukan &lt;tariqt@nvidia.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@nvidia.com&gt;
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>net/mlx5e: Add MACsec TX steering rules</title>
<updated>2022-09-07T13:02:08Z</updated>
<author>
<name>Lior Nahmanson</name>
<email>liorna@nvidia.com</email>
</author>
<published>2022-09-06T05:21:21Z</published>
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<id>urn:sha1:e467b283ffd50cf15b84c73eef68787e257eaed5</id>
<content type='text'>
Tx flow steering consists of two flow tables (FTs).

The first FT (crypto table) has two fixed rules:
One default miss rule so non MACsec offloaded packets bypass the MACSec
tables, another rule to make sure that MACsec key exchange (MKE) traffic
passes unencrypted as expected (matched of ethertype).
On each new MACsec offload flow, a new MACsec rule is added.
This rule is matched on metadata_reg_a (which contains the id of the
flow) and invokes the MACsec offload action on match.

The second FT (check table) has two fixed rules:
One rule for verifying that the previous offload actions were
finished successfully and packet need to be transmitted.
Another default rule for dropping packets that were failed in the
offload actions.

The MACsec FTs should be created on demand when the first MACsec rule is
added and destroyed when the last MACsec rule is deleted.

Signed-off-by: Lior Nahmanson &lt;liorna@nvidia.com&gt;
Reviewed-by: Raed Salem &lt;raeds@nvidia.com&gt;
Signed-off-by: Raed Salem &lt;raeds@nvidia.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@nvidia.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net/mlx5e: Fix build warning, detected write beyond size of field</title>
<updated>2022-03-22T23:48:56Z</updated>
<author>
<name>Saeed Mahameed</name>
<email>saeedm@nvidia.com</email>
</author>
<published>2022-03-22T17:22:24Z</published>
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<id>urn:sha1:2af7e566a8616c278e1d7287ce86cd3900bed943</id>
<content type='text'>
When merged with Linus tree, the cited patch below will cause the
following build warning:

In function 'fortify_memset_chk',
    inlined from 'mlx5e_xmit_xdp_frame' at drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c:438:3:
include/linux/fortify-string.h:242:25: error: call to '__write_overflow_field' declared with attribute warning: detected write beyond size of field (1st parameter); maybe use struct_group()? [-Werror=attribute-warning]
  242 |                         __write_overflow_field(p_size_field, size);
      |                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Fix that by grouping the fields to memeset in struct_group() to avoid
the false alarm.

Fixes: 9ded70fa1d81 ("net/mlx5e: Don't prefill WQEs in XDP SQ in the multi buffer mode")
Reported-by: Stephen Rothwell &lt;sfr@canb.auug.org.au&gt;
Suggested-by: Stephen Rothwell &lt;sfr@canb.auug.org.au&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@nvidia.com&gt;
Link: https://lore.kernel.org/r/20220322172224.31849-1-saeed@kernel.org
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>RDMA/mlx5: Refactor get_ts_format functions to simplify code</title>
<updated>2021-06-22T06:35:16Z</updated>
<author>
<name>Aharon Landau</name>
<email>aharonl@nvidia.com</email>
</author>
<published>2021-06-16T07:57:38Z</published>
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<id>urn:sha1:9a1ac95a59d0724ffac2181a98b232c3f94f49f5</id>
<content type='text'>
QPC, SQC and RQC timestamp formats and capabilities are always equal
because they represent general hardware support. So instead of code
duplication, let's merge them into general enum and logic.

Signed-off-by: Aharon Landau &lt;aharonl@nvidia.com&gt;
Reviewed-by: Maor Gottlieb &lt;maorg@nvidia.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@nvidia.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Set QP timestamp mode to default</title>
<updated>2021-03-10T19:01:56Z</updated>
<author>
<name>Maor Gottlieb</name>
<email>maorg@nvidia.com</email>
</author>
<published>2021-03-03T12:36:16Z</published>
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<id>urn:sha1:4806f1e2fee84c053cb68cd5be5817170bf0aab6</id>
<content type='text'>
QPs which don't care from timestamp mode, should set the ts_format
to default, otherwise the QP creation could be failed if the timestamp
mode is not supported.

Fixes: 2fe8d4b87802 ("RDMA/mlx5: Fail QP creation if the device can not support the CQE TS")
Signed-off-by: Maor Gottlieb &lt;maorg@nvidia.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@nvidia.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5e: IPsec: Add TX steering rule per IPsec state</title>
<updated>2020-10-12T22:37:45Z</updated>
<author>
<name>Huy Nguyen</name>
<email>huyn@mellanox.com</email>
</author>
<published>2020-06-06T01:17:51Z</published>
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<id>urn:sha1:9b9d454ddbf0c41391ed68ea82bc3d8ff6a65074</id>
<content type='text'>
Add new FTE in TX IPsec FT per IPsec state. It has the
same matching criteria as the RX steering rule.

The IPsec FT is created/destroyed when the first/last rule
is added/deleted respectively.

Signed-off-by: Huy Nguyen &lt;huyn@mellanox.com&gt;
Reviewed-by: Boris Pismenny &lt;borisp@nvidia.com&gt;
Reviewed-by: Tariq Toukan &lt;tariqt@nvidia.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@nvidia.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: kTLS, Improve TLS params layout structures</title>
<updated>2020-06-27T20:50:46Z</updated>
<author>
<name>Tariq Toukan</name>
<email>tariqt@mellanox.com</email>
</author>
<published>2020-06-26T05:59:43Z</published>
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<id>urn:sha1:2d1b69ed65ee033aa541518cc9f6a815296ac493</id>
<content type='text'>
Add explicit WQE segment structures for the TLS static and progress
params.
According to the HW spec, TISN is not part of the progress params context,
take it out of it.
Rename the control segment tisn field as it could hold either a TIS or
a TIR number.

Signed-off-by: Tariq Toukan &lt;tariqt@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>RDMA/mlx5: Convert modify QP to use MLX5_SET macros</title>
<updated>2020-05-27T19:07:49Z</updated>
<author>
<name>Leon Romanovsky</name>
<email>leonro@mellanox.com</email>
</author>
<published>2020-05-26T11:54:38Z</published>
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<id>urn:sha1:f18e26af6aba778b888044859d9c69bb9bbc7bc1</id>
<content type='text'>
Instead of hand crafted mlx5_qp_context and mlx5_qp_path use common
MLX5_SET() macros.

Link: https://lore.kernel.org/r/20200526115440.205922-7-leon@kernel.org
Reviewed-by: Maor Gottlieb &lt;maorg@mellanox.com&gt;
Reviewed-by: Mark Zhang &lt;markz@mellanox.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@mellanox.com&gt;
Signed-off-by: Jason Gunthorpe &lt;jgg@mellanox.com&gt;
</content>
</entry>
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