<feed xmlns='http://www.w3.org/2005/Atom'>
<title>user/sven/linux.git/include/linux/mmc, branch v3.16.46</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v3.16.46</id>
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<updated>2014-05-22T12:33:30Z</updated>
<entry>
<title>mmc: sdhci: track whether preset mode is currently enabled in hardware</title>
<updated>2014-05-22T12:33:30Z</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2014-04-25T12:00:12Z</published>
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<id>urn:sha1:da91a8f9c0f56d75b35bfe2e2456187ab55b3639</id>
<content type='text'>
Track whether preset mode is currently enabled in hardware, and use that
when making decisions elsewhere in the code rather than reading the
register and checking the bit.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
Tested-by: Markus Pargmann &lt;mpa@pengutronix.de&gt;
Tested-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
Signed-off-by: Chris Ball &lt;chris@printf.net&gt;
</content>
</entry>
<entry>
<title>mmc: sdhci: cache timing information locally</title>
<updated>2014-05-22T12:33:25Z</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2014-04-25T11:59:31Z</published>
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<id>urn:sha1:d975f121011a58223c7936ab483c3374a83236c3</id>
<content type='text'>
Rather than reading back the timing information from the registers,
cache it locally.  This allows implementations to translate the UHS
timing by overriding the set_uhs_signaling() method as required
without also having to emulate the SDHCI_HOST_CONTROL2 register.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
Tested-by: Markus Pargmann &lt;mpa@pengutronix.de&gt;
Tested-by: Stephen Warren &lt;swarren@nvidia.com&gt;
[Ulf Hansson] Resolved conflict
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
Signed-off-by: Chris Ball &lt;chris@printf.net&gt;
</content>
</entry>
<entry>
<title>mmc: sdhci: convert sdhci_set_clock() into a library function</title>
<updated>2014-05-22T11:26:32Z</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2014-04-25T11:58:55Z</published>
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<id>urn:sha1:1771059cf5f9c09e37ef6315df8acf120f2642fc</id>
<content type='text'>
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
Tested-by: Markus Pargmann &lt;mpa@pengutronix.de&gt;
Tested-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
Signed-off-by: Chris Ball &lt;chris@printf.net&gt;
</content>
</entry>
<entry>
<title>mmc: sdhci: move FSL ESDHC reset handling quirk into esdhc code</title>
<updated>2014-05-22T11:26:28Z</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2014-04-25T11:57:18Z</published>
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<id>urn:sha1:0718e59ae259f7c48155b4e852d8b0632d59028e</id>
<content type='text'>
The Freescale esdhc driver is the only driver which needs the interrupt
registers restored after a reset.  Move this quirk to be part of the
ESDHC driver implementation.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
Tested-by: Markus Pargmann &lt;mpa@pengutronix.de&gt;
Tested-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
Signed-off-by: Chris Ball &lt;chris@printf.net&gt;
</content>
</entry>
<entry>
<title>mmc: sdhci: more efficient interrupt enable register handling</title>
<updated>2014-05-22T11:26:26Z</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2014-04-25T11:56:01Z</published>
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<id>urn:sha1:b537f94ce19583de1882f539a5cc49aa99260aca</id>
<content type='text'>
Rather than wasting cycles read-modify-writing the interrupt enable
registers, cache the value locally instead.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
Tested-by: Markus Pargmann &lt;mpa@pengutronix.de&gt;
Tested-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
Signed-off-by: Chris Ball &lt;chris@printf.net&gt;
</content>
</entry>
<entry>
<title>mmc: sdhci: push card_tasklet into threaded irq handler</title>
<updated>2014-05-22T11:26:25Z</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2014-04-25T11:55:51Z</published>
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<id>urn:sha1:3560db8e247aa35bc6b287ec7ec51cd41abd512e</id>
<content type='text'>
There's no requirement to have the card tasklet separate now that we
have a threaded interrupt handler, so kill this and move the called
code into the threaded part of the handler.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
Tested-by: Markus Pargmann &lt;mpa@pengutronix.de&gt;
Tested-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
Signed-off-by: Chris Ball &lt;chris@printf.net&gt;
</content>
</entry>
<entry>
<title>mmc: sdhci: convert to new SDIO IRQ handling</title>
<updated>2014-05-22T11:26:24Z</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2014-04-25T11:55:46Z</published>
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<id>urn:sha1:781e989cf593c71d26bdca74f5e77b3651fc060e</id>
<content type='text'>
Use a generic threaded interrupt handler for SDIO interrupt handling,
rather than allowing the SDIO core code to buggily spawn its own
thread.  This results in host drivers to be more in control of how
SDIO interrupts are acknowledged in the hardware, rather than having
the internals of the SDIO core placed upon them, possibly resulting
in sub-standard handling.

At least one SDHCI implementation specifies a very specific sequence
to deal with a card interrupt.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
Tested-by: Markus Pargmann &lt;mpa@pengutronix.de&gt;
Tested-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
Signed-off-by: Chris Ball &lt;chris@printf.net&gt;
</content>
</entry>
<entry>
<title>mmc: sdio_irq: rework sdio irq handling</title>
<updated>2014-05-22T11:26:03Z</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2014-04-25T11:55:30Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=bf3b5ec66bd03d66e9ea729aaca013ea1047a797'/>
<id>urn:sha1:bf3b5ec66bd03d66e9ea729aaca013ea1047a797</id>
<content type='text'>
Rather than the SDIO support spawning it's own thread for handling card
interrupts, use the generic IRQ infrastructure for this, triggering it
from the host interface's interrupt handling directly.

This avoids a race between the parent thread waiting to receive an
interrupt response from the card, and the slow startup from the sdio
irq thread, which can occur as a result of high system load (eg, while
udev is running.)

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
Tested-by: Markus Pargmann &lt;mpa@pengutronix.de&gt;
Tested-by: Stephen Warren &lt;swarren@nvidia.com&gt;
[Ulf Hansson] Resolved conflict
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
Signed-off-by: Chris Ball &lt;chris@printf.net&gt;
</content>
</entry>
<entry>
<title>mmc: core: Improve support for deferred regulators</title>
<updated>2014-05-12T22:08:24Z</updated>
<author>
<name>Tim Kryger</name>
<email>tim.kryger@linaro.org</email>
</author>
<published>2014-05-06T22:57:01Z</published>
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<id>urn:sha1:4d1f52f9a9f9a63371dba589093b3ae90fc80c3d</id>
<content type='text'>
Callers of mmc_regulator_get_supply could benefit from knowing if either
of the regulators are present but not yet available.  Since callers do
not currently examine the return value, modify this function to return
zero or -EPROBE_DEFER if either regulator get returns the same.

Furthermore, since callers check vmmc/vqmmc using IS_ERR and can deal
with absent regulators, switch to devm_regulator_get_optional. This has
the added benefit of allowing this function to behave correctly even in
the !CONFIG_REGULATOR case such that the stub can be removed.

Signed-off-by: Tim Kryger &lt;tim.kryger@linaro.org&gt;
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
Signed-off-by: Chris Ball &lt;chris@printf.net&gt;
</content>
</entry>
<entry>
<title>mmc: add support for HS400 mode of eMMC5.0</title>
<updated>2014-05-12T22:06:06Z</updated>
<author>
<name>Seungwon Jeon</name>
<email>tgih.jun@samsung.com</email>
</author>
<published>2014-04-23T08:14:58Z</published>
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<id>urn:sha1:0a5b6438ee482696360bb013e67b8488f63d3e9e</id>
<content type='text'>
This patch adds HS400 mode support for eMMC5.0 device.  HS400 mode is high
speed DDR interface timing from HS200.  Clock frequency is up to 200MHz
and only 8-bit bus width is supported. In addition, tuning process of
HS200 is required to synchronize the command response on the CMD line
because CMD input timing for HS400 mode is the same as HS200 mode.

Signed-off-by: Seungwon Jeon &lt;tgih.jun@samsung.com&gt;
Reviewed-by: Jackey Shen &lt;jackey.shen@amd.com&gt;
Tested-by: Jaehoon Chung &lt;jh80.chung@samsung.com&gt;
Acked-by: Jaehoon Chung &lt;jh80.chung@samsung.com&gt;
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
Signed-off-by: Chris Ball &lt;chris@printf.net&gt;
</content>
</entry>
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