<feed xmlns='http://www.w3.org/2005/Atom'>
<title>user/sven/linux.git/include/linux/mtd/nand.h, branch v3.10.97</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v3.10.97</id>
<link rel='self' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v3.10.97'/>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/'/>
<updated>2013-04-05T12:22:59Z</updated>
<entry>
<title>mtd: nand: subpage write support for hardware based ECC schemes</title>
<updated>2013-04-05T12:22:59Z</updated>
<author>
<name>Gupta, Pekon</name>
<email>pekon@ti.com</email>
</author>
<published>2013-03-15T12:25:53Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=837a6ba4f3b6d23026674e6af6b6849a4634fff9'/>
<id>urn:sha1:837a6ba4f3b6d23026674e6af6b6849a4634fff9</id>
<content type='text'>
This patch adds support for subpage (partial-page) writes when using
hardware based ECC schemes.
Advantages:
(1) reduces storage overhead when using file-systems like UBIFS, which
store LEB header at page-size granularity.
(2) allows independent subpage writes, thereby increasing NAND storage
efficiency for non-page aligned data.
+ updated cafe_nand and lpc32xx_mlc NAND drivers for change in
chip-&gt;write_page interface.

Signed-off-by: Gupta, Pekon &lt;pekon@ti.com&gt;
Signed-off-by: Artem Bityutskiy &lt;artem.bityutskiy@linux.intel.com&gt;
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>mtd: nand_ids: improve LEGACY_ID_NAND macro a bit</title>
<updated>2013-04-05T12:21:41Z</updated>
<author>
<name>Artem Bityutskiy</name>
<email>artem.bityutskiy@linux.intel.com</email>
</author>
<published>2013-03-19T08:29:26Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=5bfa9b71a2d6642506e2dfdf49a66620f54f1d92'/>
<id>urn:sha1:5bfa9b71a2d6642506e2dfdf49a66620f54f1d92</id>
<content type='text'>
Notice that all the flashes belonging to the "legacy ID" class have 512 bytes
NAND page. This means we may simplify the 'LEGACY_ID_NAND()' macro as well as
the NAND ID table a little.

Signed-off-by: Artem Bityutskiy &lt;artem.bityutskiy@linux.intel.com&gt;
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>mtd: add new fields to nand_flash_dev{}</title>
<updated>2013-04-05T12:20:29Z</updated>
<author>
<name>Huang Shijie</name>
<email>b32955@freescale.com</email>
</author>
<published>2013-03-15T03:00:59Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=f22d5f638b0ea40e7cceb4639a608bd2c3eff97c'/>
<id>urn:sha1:f22d5f638b0ea40e7cceb4639a608bd2c3eff97c</id>
<content type='text'>
As time goes on, we begin to meet the situation that we can not get enough
information from some nand chips's id data. Take some Toshiba's nand chips
for example. I have 4 Toshiba's nand chips in my hand:
	TC58NVG2S0F, TC58NVG3S0F, TC58NVG5D2, TC58NVG6D2

When we read these chips' datasheets, we will get the geometry of these chips:
	TC58NVG2S0F : 4096 + 224
	TC58NVG3S0F : 4096 + 232
	TC58NVG5D2  : 8192 + 640
	TC58NVG6D2  : 8192 + 640

But we can not parse out the correct oob size for these chips from the id data.

This patch adds some new fields to the nand_flash_dev{}:
  @id_len: the valid length of the id data. See the comments in
           nand_id_has_period()
  @oobsize: the oob size.

Signed-off-by: Huang Shijie &lt;b32955@freescale.com&gt;
Reviewed-by: Brian Norris &lt;computersforpeace@gmail.com&gt;
Signed-off-by: Artem Bityutskiy &lt;artem.bityutskiy@linux.intel.com&gt;
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>mtd: introduce a macro for max NAND ID sequence length</title>
<updated>2013-04-05T12:15:06Z</updated>
<author>
<name>Artem Bityutskiy</name>
<email>artem.bityutskiy@linux.intel.com</email>
</author>
<published>2013-03-14T07:57:23Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=53552d22bfe1f83f69f18eddae2f1d96249440f3'/>
<id>urn:sha1:53552d22bfe1f83f69f18eddae2f1d96249440f3</id>
<content type='text'>
Introduce a helpful macro for the maximum NAND ID sequence length instead of
using the "8" magic number.

Signed-off-by: Artem Bityutskiy &lt;artem.bityutskiy@linux.intel.com&gt;
Acked-by: Huang Shijie &lt;shijie8@gmail.com&gt;
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>mtd: nand: use more reasonable integer types</title>
<updated>2013-04-05T12:15:00Z</updated>
<author>
<name>Artem Bityutskiy</name>
<email>artem.bityutskiy@linux.intel.com</email>
</author>
<published>2013-03-13T11:45:00Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=ecb42fea59cf2d1e7160c5c7e707120e0e6714db'/>
<id>urn:sha1:ecb42fea59cf2d1e7160c5c7e707120e0e6714db</id>
<content type='text'>
Use 'unsigned int' instead of 'unsigned long' in the NAND chip description data
structure, because 32-bits is more than enough for our purposes. We do not need
64-bits, which is what we end up on 64-bit architectures. We declare many
instances of this data structure, so this should help saving some amount of
memory.

Signed-off-by: Artem Bityutskiy &lt;artem.bityutskiy@linux.intel.com&gt;
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>mtd: nand: provision full ID support</title>
<updated>2013-04-05T11:04:22Z</updated>
<author>
<name>Artem Bityutskiy</name>
<email>artem.bityutskiy@linux.intel.com</email>
</author>
<published>2013-03-04T14:26:56Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=8e12b474f9a2349bcaebda65bdc38e8398ff408e'/>
<id>urn:sha1:8e12b474f9a2349bcaebda65bdc38e8398ff408e</id>
<content type='text'>
Up until now we identified NAND chips by the 'device ID' part of the full chip
ID array, which is the second full ID array byte. However, the newest flashes
use the same device ID for chips with identical page and eraseblock sizes, but
different OOB sizes. And unfortunately, it is not clear if there is a
"standard" way to fetch the OOB size from chip's full ID array. Here is an
example:

Toshiba TC58NVG2S0F: 0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08
Toshiba TC58NVG3S0F: 0x98, 0xd3, 0x90, 0x26, 0x76, 0x15, 0x02, 0x08

The first one is a 512MiB NAND chip with 4KiB NAND pages, 256KiB eraseblock
size and 224 bytes OOB. The second one is a 1GiB NAND chip with the same page
and eraseblock sizes, but with 232 bytes OOB.

This means that we have to store full ID in our NAND flashes table in order to
distinguish between these 2.

This patch adds the 'id[8]' field to the 'struct nand_flash_dev' structure, and
it makes it to be a part of anonymous union, where the second member is a
structure containing the 'mfr_id' and 'dev_id' bytes. The union makes sure that
'mfr_id' refers the same RAM address as 'id[0]' and 'dev_id' refers the same
RAM address as 'id[1]'. The only motivation for the union is an assumption that
'type-&gt;dev_id' is more readable than 'type-&gt;id[1]'.

Signed-off-by: Artem Bityutskiy &lt;artem.bityutskiy@linux.intel.com&gt;
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>mtd: nand_ids: introduce helper macros</title>
<updated>2013-04-05T11:03:47Z</updated>
<author>
<name>Artem Bityutskiy</name>
<email>artem.bityutskiy@linux.intel.com</email>
</author>
<published>2013-03-04T13:39:18Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=8dbfae1ef04311ba19d6b6c9a4d8fdddbb90ab0f'/>
<id>urn:sha1:8dbfae1ef04311ba19d6b6c9a4d8fdddbb90ab0f</id>
<content type='text'>
Introduce helper macros for defining NAND chips. These macros do not really add
much value in the current code-base. However, we are going to add full ID
support which adds some more complexity to the table, and helper macros become
useful for readability.

Signed-off-by: Artem Bityutskiy &lt;artem.bityutskiy@linux.intel.com&gt;
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>mtd: nand: rename the id field of 'struct nand_flash_dev'</title>
<updated>2013-04-05T11:02:41Z</updated>
<author>
<name>Artem Bityutskiy</name>
<email>artem.bityutskiy@linux.intel.com</email>
</author>
<published>2013-03-04T14:05:00Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=68aa352de28235bccdcee96ddf49f7628e93ec6f'/>
<id>urn:sha1:68aa352de28235bccdcee96ddf49f7628e93ec6f</id>
<content type='text'>
The 'id' is a bit confusing name because NAND IDs are multi-byte. Re-name
it to 'dev_id' to make it clear that this is the "device ID" part (the second
byte).

While on it, clean-up the commentary for 'struct nand_flash_dev'.

Signed-off-by: Artem Bityutskiy &lt;artem.bityutskiy@linux.intel.com&gt;
Acked-by: Brian Norris &lt;computersforpeace@gmail.com&gt;
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>mtd: nand: use NAND_HAS_CACHEPROG</title>
<updated>2013-04-05T11:02:19Z</updated>
<author>
<name>Artem Bityutskiy</name>
<email>artem.bityutskiy@linux.intel.com</email>
</author>
<published>2013-03-04T12:56:18Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=3239a6cdef0be60ec2dadc501cf385dc419d7452'/>
<id>urn:sha1:3239a6cdef0be60ec2dadc501cf385dc419d7452</id>
<content type='text'>
We have this unused macro, let's use it and justify its existence.

Signed-off-by: Artem Bityutskiy &lt;artem.bityutskiy@linux.intel.com&gt;
Acked-by: Brian Norris &lt;computersforpeace@gmail.com&gt;
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>mtd: nand: remove NAND_COPYBACK macro</title>
<updated>2013-04-05T11:01:58Z</updated>
<author>
<name>Artem Bityutskiy</name>
<email>artem.bityutskiy@linux.intel.com</email>
</author>
<published>2013-03-04T12:52:25Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=88ad4b162adb3821815d0098987040fca26c7d80'/>
<id>urn:sha1:88ad4b162adb3821815d0098987040fca26c7d80</id>
<content type='text'>
It is unused.

Signed-off-by: Artem Bityutskiy &lt;artem.bityutskiy@linux.intel.com&gt;
Acked-by: Brian Norris &lt;computersforpeace@gmail.com&gt;
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
</feed>
