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<title>user/sven/linux.git/include/linux/mtd, branch v5.13.16</title>
<subtitle>Linux Kernel
</subtitle>
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<updated>2021-04-16T18:30:54Z</updated>
<entry>
<title>mtd: core: Constify buf in mtd_write_user_prot_reg()</title>
<updated>2021-04-16T18:30:54Z</updated>
<author>
<name>Tudor Ambarus</name>
<email>tudor.ambarus@microchip.com</email>
</author>
<published>2021-04-03T06:09:31Z</published>
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<id>urn:sha1:1df1fc8c62f7527d953c7f3869930067bf5b3f29</id>
<content type='text'>
The write buffer comes from user and should be const.
Constify write buffer in mtd core and across all _write_user_prot_reg()
users. cfi_cmdset_{0001, 0002} and onenand_base will pay the cost of an
explicit cast to discard the const qualifier since the beginning, since
they are using an otp_op_t function prototype that is used for both reads
and writes. mtd_dataflash and SPI NOR will benefit of the const buffer
because they are using different paths for writes and reads.

Signed-off-by: Tudor Ambarus &lt;tudor.ambarus@microchip.com&gt;
Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Link: https://lore.kernel.org/linux-mtd/20210403060931.7119-1-tudor.ambarus@microchip.com
</content>
</entry>
<entry>
<title>Merge tag 'nand/for-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux into mtd/next</title>
<updated>2021-04-15T19:14:51Z</updated>
<author>
<name>Richard Weinberger</name>
<email>richard@nod.at</email>
</author>
<published>2021-04-15T19:14:51Z</published>
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<id>urn:sha1:ef4ed780d005d65b1a70ba7803233cace93a73ac</id>
<content type='text'>
MTD core:
* Handle possible -EPROBE_DEFER from parse_mtd_partitions()

NAND core:
* Fix error handling in nand_prog_page_op() (x2)
* Add a helper to retrieve the number of ECC bytes per step
* Add a helper to retrieve the number of ECC steps
* Let ECC engines advertize the exact number of steps
* ECC Hamming:
  - Populate the public nsteps field
  - Use the public nsteps field
* ECC BCH:
  - Populate the public nsteps field
  - Use the public nsteps field

Raw NAND core:
* Add support for secure regions in NAND memory
* Try not to use the ECC private structures
* Remove duplicate include in rawnand.h
* BBT:
  - Skip bad blocks when searching for the BBT in NAND

Raw NAND controller drivers:
* Qcom:
  - Convert bindings to YAML
  - Use dma_mapping_error() for error check
  - Add missing nand_cleanup() in error path
  - Return actual error code instead of -ENODEV
  - Update last code word register
  - Add helper to configure location register
  - Rename parameter name in macro
  - Add helper to check last code word
  - Convert nandc to chip in Read/Write helper
  - Update register macro name for 0x2c offset
* GPMI:
  - Fix a double free in gpmi_nand_init
* Rockchip:
  - Use flexible-array member instead of zero-length array
* Atmel:
  - Update ecc_stats.corrected counter
* MXC:
  - Remove unneeded of_match_ptr()
* R852:
  - replace spin_lock_irqsave by spin_lock in hard IRQ
* Brcmnand:
  - Move to polling in pio mode on oops write
  - Read/write oob during EDU transfer
  - Fix OOB R/W with Hamming ECC
* FSMC:
  - Fix error code in fsmc_nand_probe()
* OMAP:
  - Use ECC information from the generic structures

SPI-NAND core:
* Add missing MODULE_DEVICE_TABLE()

SPI-NAND drivers:
* gigadevice: Support GD5F1GQ5UExxG
</content>
</entry>
<entry>
<title>Merge tag 'spi-nor/for-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux into mtd/next</title>
<updated>2021-04-15T19:13:51Z</updated>
<author>
<name>Richard Weinberger</name>
<email>richard@nod.at</email>
</author>
<published>2021-04-15T19:13:51Z</published>
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<id>urn:sha1:256437ebda641c49abbbe919becc16f75848380b</id>
<content type='text'>
SPI NOR core changes:
- Add OTP support
- Fix module unload while an op in progress
- Add various cleanup patches

SPI NOR controller drivers changes:
- intel-spi: Move platform data header to x86 subfolder
</content>
</entry>
<entry>
<title>mtd: rawnand: Add support for secure regions in NAND memory</title>
<updated>2021-04-07T08:06:24Z</updated>
<author>
<name>Manivannan Sadhasivam</name>
<email>manivannan.sadhasivam@linaro.org</email>
</author>
<published>2021-04-02T15:01:27Z</published>
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<id>urn:sha1:13b89768275d6ca9764bf91449e4cafe46ba706b</id>
<content type='text'>
On a typical end product, a vendor may choose to secure some regions in
the NAND memory which are supposed to stay intact between FW upgrades.
The access to those regions will be blocked by a secure element like
Trustzone. So the normal world software like Linux kernel should not
touch these regions (including reading).

The regions are declared using a NAND chip DT property,
"secure-regions". So let's make use of this property in the raw NAND
core and skip access to the secure regions present in a system.

Signed-off-by: Manivannan Sadhasivam &lt;manivannan.sadhasivam@linaro.org&gt;
Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Link: https://lore.kernel.org/linux-mtd/20210402150128.29128-4-manivannan.sadhasivam@linaro.org
</content>
</entry>
<entry>
<title>mtd: spi-nor: implement OTP support for Winbond and similar flashes</title>
<updated>2021-04-02T06:32:27Z</updated>
<author>
<name>Michael Walle</name>
<email>michael@walle.cc</email>
</author>
<published>2021-03-21T23:51:39Z</published>
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<id>urn:sha1:cad3193fe9d1f0af4d05ed86693f99984409b188</id>
<content type='text'>
Use the new OTP ops to implement OTP access on Winbond flashes. Most
Winbond flashes provides up to four different OTP regions ("Security
Registers").

Winbond devices use a special opcode to read and write to the OTP
regions, just like the RDSFDP opcode. In fact, it seems that the
(undocumented) first OTP area of the newer flashes is the actual SFDP
table.

On a side note, Winbond devices also allow erasing the OTP regions as
long as the area isn't locked down.

Signed-off-by: Michael Walle &lt;michael@walle.cc&gt;
Signed-off-by: Tudor Ambarus &lt;tudor.ambarus@microchip.com&gt;
Link: https://lore.kernel.org/r/20210321235140.8308-3-michael@walle.cc
</content>
</entry>
<entry>
<title>include: linux: mtd: Remove duplicate include of nand.h</title>
<updated>2021-03-28T17:27:02Z</updated>
<author>
<name>Wan Jiabing</name>
<email>wanjiabing@vivo.com</email>
</author>
<published>2021-03-23T03:17:37Z</published>
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<id>urn:sha1:28f0be44b263ca4b59ea63c801db3830e65fbe99</id>
<content type='text'>
linux/mtd/nand.h has been included at line 17.
So we remove the duplicate one at line 21.

Signed-off-by: Wan Jiabing &lt;wanjiabing@vivo.com&gt;
Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Link: https://lore.kernel.org/linux-mtd/20210323031737.259365-1-wanjiabing@vivo.com
</content>
</entry>
<entry>
<title>mtd: add OTP (one-time-programmable) erase ioctl</title>
<updated>2021-03-28T17:24:54Z</updated>
<author>
<name>Michael Walle</name>
<email>michael@walle.cc</email>
</author>
<published>2021-03-03T20:18:19Z</published>
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<id>urn:sha1:e3c1f1c92d6ede3cfa09d6a103d3d1c1ef645e35</id>
<content type='text'>
This may sound like a contradiction but some SPI-NOR flashes really
support erasing their OTP region until it is finally locked. Having the
possibility to erase an OTP region might come in handy during
development.

The ioctl argument follows the OTPLOCK style.

Signed-off-by: Michael Walle &lt;michael@walle.cc&gt;
Acked-by: Vignesh Raghavendra &lt;vigneshr@ti.com&gt;
Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Link: https://lore.kernel.org/linux-mtd/20210303201819.2752-1-michael@walle.cc
</content>
</entry>
<entry>
<title>mtd: rawnand: remove duplicate include in rawnand.h</title>
<updated>2021-03-28T17:13:34Z</updated>
<author>
<name>Zhang Yunkai</name>
<email>zhang.yunkai@zte.com.cn</email>
</author>
<published>2021-03-13T10:57:02Z</published>
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<id>urn:sha1:7a534c5e4159f9bbac9f3c146dc78e163d8858c2</id>
<content type='text'>
'linux/mtd/nand.h' included in 'rawnand.h' is duplicated.
It is also included in the 17th line.

Signed-off-by: Zhang Yunkai &lt;zhang.yunkai@zte.com.cn&gt;
Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Link: https://lore.kernel.org/linux-mtd/20210313105702.365878-1-zhang.yunkai@zte.com.cn
</content>
</entry>
<entry>
<title>mtd: char: Get rid of Big MTD Lock</title>
<updated>2021-03-11T08:37:49Z</updated>
<author>
<name>Alexander Sverdlin</name>
<email>alexander.sverdlin@nokia.com</email>
</author>
<published>2021-02-17T21:18:45Z</published>
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<id>urn:sha1:1ad55288829c78e85bfe7d0c86d75415adf5f305</id>
<content type='text'>
Get rid of central chrdev MTD lock, which prevents simultaneous operations
on completely independent physical MTD chips. Replace it with newly
introduced per-master mutex.

Signed-off-by: Alexander Sverdlin &lt;alexander.sverdlin@nokia.com&gt;
Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Link: https://lore.kernel.org/linux-mtd/20210217211845.43364-2-alexander.sverdlin@nokia.com
</content>
</entry>
<entry>
<title>mtd: Add helper macro for register_mtd_blktrans boilerplate</title>
<updated>2021-03-11T08:37:48Z</updated>
<author>
<name>Dejin Zheng</name>
<email>zhengdejin5@gmail.com</email>
</author>
<published>2021-02-13T16:45:53Z</published>
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<id>urn:sha1:6cfeb41a825913f3dcb131d6556cc9d1c4072015</id>
<content type='text'>
This patch introduces the module_mtd_blktrans macro which is a convenience
macro for mtd blktrans modules similar to module_platform_driver.
It is intended to be used by drivers which init/exit section does nothing
but register/unregister the mtd blktrans driver. By using this macro it is
possible to eliminate a few lines of boilerplate code per mtd blktrans
driver.

Signed-off-by: Dejin Zheng &lt;zhengdejin5@gmail.com&gt;
Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Link: https://lore.kernel.org/linux-mtd/20210213164600.409061-2-zhengdejin5@gmail.com
</content>
</entry>
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