user/sven/linux.git/include/linux/mtd, branch v5.5.14

mtd: onenand: omap2: Fix errors in style

2020-01-09T19:08:15Z

Correct mispelling, spacing, and coding style flaws caught by checkpatch.pl script in the Omap2 Onenand driver . Signed-off-by: Amir Mahdi Ghorbanian Signed-off-by: Miquel Raynal

mtd: spi-nor: Set default Quad Enable method for ISSI flashes

2019-11-11T18:42:55Z

Set the default Quad Enable method for ISSI flashes. Used for ISSI flashes (IS25WP256D-JMLE) that do not support SFDP tables and can not determine the Quad Enable method by parsing BFPT. Based on code originally written by Wesley Terpstra and/or Palmer Dabbelt https://github.com/riscv/riscv-linux/commit/c94e267766d62bc9a669611c3d0c8ed5ea26569b Signed-off-by: Sagar Shrikant Kadam [tudor.ambarus@microchip.com: - rebase, split and adapt for latest spi-nor/next, - use PMC CFI ID for ISSI. According to JEP106BA, "Programmable Micro Corp" changed its name to Integrated Silicon Solution (ISSI)] Signed-off-by: Tudor Ambarus Reviewed-by: Vignesh Raghavendra

mtd: spi-nor: Rename Quad Enable methods

2019-11-11T06:56:40Z

Rename macronix_quad_enable() to a generic name: spi_nor_sr1_bit6_quad_enable(). Prepend "spi_nor_" to "sr2_bit7_quad_enable". All SPI NOR generic methods should be prepended by "spi_nor_". Signed-off-by: Tudor Ambarus Reviewed-by: Vignesh Raghavendra

mtd: spi-nor: Rename CR_QUAD_EN_SPAN to SR2_QUAD_EN_BIT1

2019-11-11T06:56:37Z

JEDEC Basic Flash Parameter Table, 15th DWORD, bits 22:20, refers to this bit as "bit 1 of the status register 2". Rename the macro accordingly. Signed-off-by: Tudor Ambarus Reviewed-by: Vignesh Raghavendra

mtd: spi-nor: Rework the disabling of block write protection

2019-11-11T06:56:19Z

spi_nor_unlock() unlocks blocks of memory or the entire flash memory array, if requested. clear_sr_bp() unlocks the entire flash memory array at boot time. This calls for some unification, clear_sr_bp() is just an optimization for the case when the unlock request covers the entire flash size. Get rid of clear_sr_bp() and introduce spi_nor_unlock_all(), which is just a call to spi_nor_unlock() for the entire flash memory array. This fixes a bug that was present in spi_nor_spansion_clear_sr_bp(). When the QE bit was zero, we used the Write Status (01h) command with one data byte, which might cleared the Status Register 2. We now always use the Write Status (01h) command with two data bytes when SNOR_F_HAS_16BIT_SR is set, to avoid clearing the Status Register 2. The SNOR_F_NO_READ_CR case is treated as well. When the flash doesn't support the CR Read command, we make an assumption about the value of the QE bit. In spi_nor_init(), call spi_nor_quad_enable() first, then spi_nor_unlock_all(), so that at the spi_nor_unlock_all() time we can be sure the QE bit has value one, because of the previous call to spi_nor_quad_enable(). Get rid of the MFR handling and implement specific manufacturer default_init() fixup hooks. Note that this changes a bit the logic for the SNOR_MFR_ATMEL, SNOR_MFR_INTEL and SNOR_MFR_SST cases. Before this patch, the Atmel, Intel and SST chips did not set the locking ops, but unlocked the entire flash at boot time, while now they are setting the locking ops to stm_locking_ops. This should work, since the disable of the block protection at the boot time used the same Status Register bits to unlock the flash, as in the stm_locking_ops case. Suggested-by: Boris Brezillon Signed-off-by: Tudor Ambarus Reviewed-by: Vignesh Raghavendra

mtd: spi-nor: Fix clearing of QE bit on lock()/unlock()

2019-11-11T06:55:25Z

Make sure that when doing a lock() or an unlock() operation we don't clear the QE bit from Status Register 2. JESD216 revB or later offers information about the *default* Status Register commands to use (see BFPT DWORDS[15], bits 22:20). In this standard, Status Register 1 refers to the first data byte transferred on a Read Status (05h) or Write Status (01h) command. Status register 2 refers to the byte read using instruction 35h. Status register 2 is the second byte transferred in a Write Status (01h) command. Industry naming and definitions of these Status Registers may differ. The definitions are described in JESD216B, BFPT DWORDS[15], bits 22:20. There are cases in which writing only one byte to the Status Register 1 has the side-effect of clearing Status Register 2 and implicitly the Quad Enable bit. This side-effect is hit just by the BFPT_DWORD15_QER_SR2_BIT1_BUGGY and BFPT_DWORD15_QER_SR2_BIT1 cases. Suggested-by: Boris Brezillon Signed-off-by: Tudor Ambarus Reviewed-by: Vignesh Raghavendra

mtd: spi-nor: Introduce 'struct spi_nor_controller_ops'

2019-10-23T06:27:21Z

Move all SPI NOR controller driver specific ops in a dedicated structure. 'struct spi_nor' becomes lighter. Use size_t for lengths in 'int (*write_reg)()' and 'int (*read_reg)()'. Rename wite/read_buf to buf, the name of the functions are suggestive enough. Constify buf in int (*write_reg). Comply with these changes in the SPI NOR controller drivers. Suggested-by: Boris Brezillon Signed-off-by: Tudor Ambarus Reviewed-by: Boris Brezillon

Merge tag 'mtd/for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux

2019-09-21T17:59:54Z

Pull MTD updates from Richard Weinberger: "MTD core changes: - add debugfs nodes for querying the flash name and id - mtd parser reorganization SPI NOR core changes: - always use bounce buffer for register read/writes - move m25p80 code in spi-nor.c - rework hwcaps selection for the spi-mem case - rework the core in order to move the manufacturer specific code out of it: - regroup flash parameters in 'struct spi_nor_flash_parameter' - add default_init() and post_sfdp() hooks to tweak the flash parameters - introduce the ->set_4byte(), ->convert_addr() and ->setup() methods, to deal with manufacturer specific code - rework the SPI NOR lock/unlock logic - fix an error code in spi_nor_read_raw() - fix a memory leak bug - enable the debugfs for the partname and partid - add support for few flashes SPI NOR controller drivers changes: - intel-spi: - Whitelist 4B read commands - Add support for Intel Tiger Lake SPI serial flash - aspeed-smc: Add of_node_put() - hisi-sfc: add of_node_put() - cadence-quadspi: Fix QSPI RCU Schedule Stall NAND core: - Fixing typos - Adding missing of_node_put() in various drivers Raw NAND controller drivers: - Macronix: new controller driver - Omap2: fix the number of bitflips returned - Brcmnand: fix a pointer not iterating over all the page chunks - W90x900: driver removed - Onenand: fix a memory leak - Sharpsl: missing include guard - STM32: avoid warnings when building with W=1 - Ingenic: fix a coccinelle warning - r852: call a helper to simplify the code CFI core: - Kill useless initializer in mtd_do_chip_probe() - Fix a rare write failure seen on some cfi_cmdset_0002 compliant Parallel NORs - Bunch of cleanups for cfi_cmdset_0002 driver's write functions by Tokunori Ikegami" * tag 'mtd/for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (77 commits) mtd: pmc551: Remove set but not used variable 'soff_lo' mtd: cfi_cmdset_0002: Fix do_erase_chip() to get chip as erasing mode mtd: sm_ftl: Fix memory leak in sm_init_zone() error path mtd: parsers: Move CMDLINE parser mtd: parsers: Move OF parser mtd: parsers: Move BCM63xx parser mtd: parsers: Move BCM47xx parser mtd: parsers: Move TI AR7 parser mtd: pismo: Simplify getting the adapter of a client mtd: phram: Module parameters add writable permissions mtd: pxa2xx: Use ioremap_cache insted of ioremap_cached mtd: spi-nor: Rename "n25q512a" to "mt25qu512a (n25q512a)" mtd: spi-nor: Add support for mt35xu02g mtd: rawnand: omap2: Fix number of bitflips reporting with ELM mtd: rawnand: brcmnand: Fix ecc chunk calculation for erased page bitfips mtd: spi-nor: remove superfluous pass of nor->info->sector_size mtd: spi-nor: enable the debugfs for the partname and partid mtd: mtdcore: add debugfs nodes for querying the flash name and id mtd: spi-nor: hisi-sfc: Add of_node_put() before break mtd: spi-nor: aspeed-smc: Add of_node_put() ...

Merge tag 'spi-nor/for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux into mtd/for-5.4

2019-09-15T21:00:55Z

MTD core changes: - add debugfs nodes for querying the flash name and id SPI NOR core changes: - always use bounce buffer for register read/writes - move m25p80 code in spi-nor.c - rework hwcaps selection for the spi-mem case - rework the core in order to move the manufacturer specific code out of it: - regroup flash parameters in 'struct spi_nor_flash_parameter' - add default_init() and post_sfdp() hooks to tweak the flash parameters - introduce the ->set_4byte(), ->convert_addr() and ->setup() methods, to deal with manufacturer specific code - rework the SPI NOR lock/unlock logic - fix an error code in spi_nor_read_raw() - fix a memory leak bug - enable the debugfs for the partname and partid - add support for few flashes SPI NOR controller drivers changes: - intel-spi: - Whitelist 4B read commands - Add support for Intel Tiger Lake SPI serial flash - aspeed-smc: Add of_node_put() - hisi-sfc: Add of_node_put() - cadence-quadspi: Fix QSPI RCU Schedule Stall

mtd: Kill mount_mtd()

2019-09-05T18:34:26Z

Kill mount_mtd() as it has now been replaced by vfs_get_mtd_super() in the new mount API and nothing now uses it. Signed-off-by: David Howells cc: David Woodhouse cc: Brian Norris cc: Boris Brezillon cc: Marek Vasut cc: Richard Weinberger cc: linux-mtd@lists.infradead.org Signed-off-by: Al Viro