user/sven/linux.git/include/linux/pci_ids.h, branch v3.2.79

PCI: Define macro for Marvell vendor ID

2014-01-03T04:33:24Z

commit 8e7ee6f5dfb56a32da760d990be908ed35b1c5bf upstream. Define PCI_VENDOR_ID_MARVELL_EXT macro for 0x1b4b vendor ID Signed-off-by: Xiangliang Yu Signed-off-by: Myron Stowe Signed-off-by: Bjorn Helgaas Signed-off-by: Ben Hutchings

PCI: Reduce Ricoh 0xe822 SD card reader base clock frequency to 50MHz

2013-01-16T01:13:13Z

commit 812089e01b9f65f90fc8fc670d8cce72a0e01fbb upstream. Otherwise it fails like this on cards like the Transcend 16GB SDHC card: mmc0: new SDHC card at address b368 mmcblk0: mmc0:b368 SDC 15.0 GiB mmcblk0: error -110 sending status command, retrying mmcblk0: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0xb0 Tested on my Lenovo x200 laptop. [bhelgaas: changelog] Signed-off-by: Andy Lutomirski Signed-off-by: Bjorn Helgaas Acked-by: Chris Ball CC: Manoj Iyer Signed-off-by: Ben Hutchings

hpsa: gen8plus Smart Array IDs

2013-01-03T03:33:54Z

commit fe0c9610bb68dd0aad1017456f5e3c31264d70c2 upstream. Signed-off-by: James Bottomley Signed-off-by: Ben Hutchings

serial: set correct baud_base for EXSYS EX-41092 Dual 16950

2012-10-17T02:49:01Z

commit 26e8220adb0aec43b7acafa0f1431760eee28522 upstream. Apparently the same card model has two IDs, so this patch complements the commit 39aced68d664291db3324d0fcf0985ab5626aac2 adding the missing one. Signed-off-by: Flavio Leitner Signed-off-by: Greg Kroah-Hartman [bwh: Backported to 3.2: adjust filename] Signed-off-by: Ben Hutchings

bnx2x: fix 57840_MF pci id

2012-09-19T14:04:58Z

[ Upstream commit 5c879d2094946081af934739850c7260e8b25d3c ] Commit c3def943c7117d42caaed3478731ea7c3c87190e have added support for new pci ids of the 57840 board, while failing to change the obsolete value in 'pci_ids.h'. This patch does so, allowing the probe of such devices. Signed-off-by: Yuval Mintz Signed-off-by: Eilon Greenstein Signed-off-by: David S. Miller Signed-off-by: Ben Hutchings

x86, amd: Fix up numa_node information for AMD CPU family 15h model 0-0fh northbridge functions

2011-12-05T17:13:11Z

I've received complaints that the numa_node attribute for family 15h model 00-0fh (e.g. Interlagos) northbridge functions shows -1 instead of the proper node ID. Correct this with attached quirks (similar to quirks for other AMD CPU families used in multi-socket systems). Signed-off-by: Andreas Herrmann Cc: Frank Arnold Cc: Borislav Petkov Link: http://lkml.kernel.org/r/20111202072143.GA31916@alberich.amd.com Signed-off-by: Ingo Molnar

[libata] ahci: Add ASMedia ASM1061 support

2011-11-09T06:47:36Z

Signed-off-by: Keng-Yu Lin Signed-off-by: Jeff Garzik

[SCSI] mv_sas: OCZ RevoDrive3 & zDrive R4 support

2011-10-31T09:29:01Z

In the OCZ RevoDrive3/zDrive R4 series, the "OCZ SuperScale Storage Controller" with "Virtualized Controller Architecture 2.0" really seems to be a Marvell 88SE9485 part, with OCZ firmware/BIOS. Developed and tested on OCZ RevoDrive3 120GB [PCI 1b85:1021] Should work on: - OCZ RevoDrive3 (2x SandForce 2281) - OCZ RevoDrive3 X2 (4x SandForce 2281) - OCZ zDrive R4 CM84 (4x SandForce 2281) - OCZ zDrive R4 CM88 (8x SandForce 2281) - OCZ zDrive R4 RM84 (4x SandForce 2582) - OCZ zDrive R4 RM88 (8x SandForce 2582) All of this because a friend recently bought a OCZ RevoDrive3 and was bitten by the lack of Linux support. Notes from testing: ------------------- - SMART works. - VPD Device Identification is "OCZ-REVODRIVE3" - Thin provisioning/TRIM seems to be implemented as WRITE SAME UNMAP, with deterministic (non-zero) read after TRIM, but I'm not sure if it works 100% in my testing. - Some of the tuning in the firmware seems to ensure much better performance when in a RAID0 setup than using the two devices seperately. I have not tested booting from the SSD, because all of this was developed and tested remotely from the actual hardware. Signed-off-by: Robin H. Johnson Thanks-To: Gordon Pritchard Acked-by: Xiangliang Yu Signed-off-by: James Bottomley

PCI: Add Solarflare vendor ID and SFC4000 device IDs

2011-10-14T16:05:27Z

These will be shared between the sfc driver and a PCI quirk. Signed-off-by: Ben Hutchings Signed-off-by: Jesse Barnes

Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx

2011-08-05T02:43:43Z

* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: dmaengine: use DEFINE_IDR for static initialization ioat: fix xor_idx_to_desc Avoid section type conflict in dma/ioat/dma_v3.c ioat: Adding PCI IDs for IOAT devices on SandyBridge platforms