<feed xmlns='http://www.w3.org/2005/Atom'>
<title>user/sven/linux.git/include/linux/pci_regs.h, branch v3.2</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v3.2</id>
<link rel='self' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v3.2'/>
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<updated>2011-10-14T16:05:35Z</updated>
<entry>
<title>PCI: Add support for PASID capability</title>
<updated>2011-10-14T16:05:35Z</updated>
<author>
<name>Joerg Roedel</name>
<email>joerg.roedel@amd.com</email>
</author>
<published>2011-09-27T13:57:16Z</published>
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<id>urn:sha1:086ac11f6435c9dc2fe5025fc8ea3a1dbca273d6</id>
<content type='text'>
Devices supporting Process Address Space Identifiers
(PASIDs) can use an IOMMU to access multiple IO address
spaces at the same time. A PCIe device indicates support for
this feature by implementing the PASID capability. This
patch adds support for the capability to the Linux kernel.

Reviewed-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Signed-off-by: Joerg Roedel &lt;joerg.roedel@amd.com&gt;
Signed-off-by: Jesse Barnes &lt;jbarnes@virtuousgeek.org&gt;
</content>
</entry>
<entry>
<title>PCI: Add implementation for PRI capability</title>
<updated>2011-10-14T16:05:34Z</updated>
<author>
<name>Joerg Roedel</name>
<email>joerg.roedel@amd.com</email>
</author>
<published>2011-09-27T13:57:15Z</published>
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<id>urn:sha1:c320b976d7837c561ce4aa49dfe0a64f0e527ce4</id>
<content type='text'>
Implement the necessary functions to handle PRI capabilities
on PCIe devices. With PRI devices behind an IOMMU can signal
page fault conditions to software and recover from such
faults.

Reviewed-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Signed-off-by: Joerg Roedel &lt;joerg.roedel@amd.com&gt;
Signed-off-by: Jesse Barnes &lt;jbarnes@virtuousgeek.org&gt;
</content>
</entry>
<entry>
<title>PCI: add latency tolerance reporting enable/disable support</title>
<updated>2011-05-11T22:18:53Z</updated>
<author>
<name>Jesse Barnes</name>
<email>jbarnes@virtuousgeek.org</email>
</author>
<published>2011-01-14T16:53:04Z</published>
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<id>urn:sha1:51c2e0a7e5bc7ed1384cc68cfb95e702571500c9</id>
<content type='text'>
Latency tolerance reporting allows devices to send messages to the root
complex indicating their latency tolerance for snooped &amp; unsnooped
memory transactions.  Add support for enabling &amp; disabling this
feature, along with a routine to set the max latencies a device should
send upstream.

Signed-off-by: Jesse Barnes &lt;jbarnes@virtuousgeek.org&gt;
</content>
</entry>
<entry>
<title>PCI: add OBFF enable/disable support</title>
<updated>2011-05-11T22:18:48Z</updated>
<author>
<name>Jesse Barnes</name>
<email>jbarnes@virtuousgeek.org</email>
</author>
<published>2011-01-10T20:46:36Z</published>
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<id>urn:sha1:48a92a8179b3e677fac07db7bd109e68f020468c</id>
<content type='text'>
OBFF (optimized buffer flush/fill), where supported, can help improve
energy efficiency by giving devices information about when interrupts
and other activity will have a reduced power impact.  It requires
support from both the device and system (i.e. not only does the device
need to respond to OBFF messages, but the platform must be capable of
generating and routing them to the end point).

Signed-off-by: Jesse Barnes &lt;jbarnes@virtuousgeek.org&gt;
</content>
</entry>
<entry>
<title>PCI: add ID-based ordering enable/disable support</title>
<updated>2011-05-11T22:18:40Z</updated>
<author>
<name>Jesse Barnes</name>
<email>jbarnes@virtuousgeek.org</email>
</author>
<published>2010-10-19T20:07:57Z</published>
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<id>urn:sha1:b48d4425b602f5f4978299474743dbea130d940d</id>
<content type='text'>
Add support to allow drivers to enable/disable ID-based ordering.  Where
supported, ID-based ordering can significantly improve the latency of
individual requests by preventing them from queueing up behind unrelated
traffic.

Signed-off-by: Jesse Barnes &lt;jbarnes@virtuousgeek.org&gt;
</content>
</entry>
<entry>
<title>Fix common misspellings</title>
<updated>2011-03-31T14:26:23Z</updated>
<author>
<name>Lucas De Marchi</name>
<email>lucas.demarchi@profusion.mobi</email>
</author>
<published>2011-03-31T01:57:33Z</published>
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<id>urn:sha1:25985edcedea6396277003854657b5f3cb31a628</id>
<content type='text'>
Fixes generated by 'codespell' and manually reviewed.

Signed-off-by: Lucas De Marchi &lt;lucas.demarchi@profusion.mobi&gt;
</content>
</entry>
<entry>
<title>PCI/PCIe: Clear Root PME Status bits early during system resume</title>
<updated>2010-12-23T20:54:03Z</updated>
<author>
<name>Rafael J. Wysocki</name>
<email>rjw@sisk.pl</email>
</author>
<published>2010-12-19T14:57:16Z</published>
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<id>urn:sha1:fe31e69740eddc7316071ed5165fed6703c8cd12</id>
<content type='text'>
I noticed that PCI Express PMEs don't work on my Toshiba Portege R500
after the system has been woken up from a sleep state by a PME
(through Wake-on-LAN).  After some investigation it turned out that
the BIOS didn't clear the Root PME Status bit in the root port that
received the wakeup PME and since the Requester ID was also set in
the port's Root Status register, any subsequent PMEs didn't trigger
interrupts.

This problem can be avoided by clearing the Root PME Status bits in
all PCI Express root ports during early resume.  For this purpose,
add an early resume routine to the PCIe port driver and make this
driver be always registered, even if pci_ports_disable is set (in
which case the driver's only function is to provide the early
resume callback).

Signed-off-by: Rafael J. Wysocki &lt;rjw@sisk.pl&gt;
Signed-off-by: Jesse Barnes &lt;jbarnes@virtuousgeek.org&gt;
</content>
</entry>
<entry>
<title>PCI: Add mask bit definition for MSI-X table</title>
<updated>2010-12-23T20:53:08Z</updated>
<author>
<name>Sheng Yang</name>
<email>sheng@linux.intel.com</email>
</author>
<published>2010-11-11T07:46:55Z</published>
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<id>urn:sha1:8d805286968811223cca002134ba3d81244d5313</id>
<content type='text'>
Then we can use it instead of magic number 1.

Reviewed-by: Hidetoshi Seto &lt;seto.hidetoshi@jp.fujitsu.com&gt;
Cc: Matthew Wilcox &lt;willy@linux.intel.com&gt;
Signed-off-by: Sheng Yang &lt;sheng@linux.intel.com&gt;
Signed-off-by: Jesse Barnes &lt;jbarnes@virtuousgeek.org&gt;
</content>
</entry>
<entry>
<title>PCI: MSI: Move MSI-X entry definition to pci_regs.h</title>
<updated>2010-12-23T20:53:07Z</updated>
<author>
<name>Sheng Yang</name>
<email>sheng@linux.intel.com</email>
</author>
<published>2010-11-11T07:46:54Z</published>
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<id>urn:sha1:00aaaef9a51a1a25c5d6d52ce510772f149a0eb0</id>
<content type='text'>
Then it can be used by others.

Reviewed-by: Hidetoshi Seto &lt;seto.hidetoshi@jp.fujitsu.com&gt;
Reviewed-by: Matthew Wilcox &lt;willy@linux.intel.com&gt;
Signed-off-by: Sheng Yang &lt;sheng@linux.intel.com&gt;
Signed-off-by: Jesse Barnes &lt;jbarnes@virtuousgeek.org&gt;
</content>
</entry>
<entry>
<title>PCI: add PCI_MSIX_TABLE/PBA defines</title>
<updated>2010-10-18T03:03:03Z</updated>
<author>
<name>Hidetoshi Seto</name>
<email>seto.hidetoshi@jp.fujitsu.com</email>
</author>
<published>2010-10-13T06:00:23Z</published>
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<id>urn:sha1:db5004195481fcb500c929bd3a0e1c0c48eec527</id>
<content type='text'>
These are already defined in pcilib's pci/header.h but not in kernel's
linux/pci_regs.h.  Copy them to avoid using magic numbers.

Signed-off-by: Hidetoshi Seto &lt;seto.hidetoshi@jp.fujitsu.com&gt;
Signed-off-by: Jesse Barnes &lt;jbarnes@virtuousgeek.org&gt;
</content>
</entry>
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