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<title>user/sven/linux.git/include/linux/phy, branch v4.0</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v4.0</id>
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<updated>2015-02-11T18:28:45Z</updated>
<entry>
<title>Merge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi</title>
<updated>2015-02-11T18:28:45Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2015-02-11T18:28:45Z</published>
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<id>urn:sha1:540a7c5061f10a07748c89b6741af90db1a07252</id>
<content type='text'>
Pull first round of SCSI updates from James Bottomley:
 "This is the usual grab bag of driver updates (hpsa, storvsc, mp2sas,
  megaraid_sas, ses) plus an assortment of minor updates.

  There's also an update to ufs which adds new phy drivers and finally a
  new logging infrastructure for SCSI"

* tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi: (114 commits)
  scsi_logging: return void for dev_printk() functions
  scsi: print single-character strings with seq_putc
  scsi: merge consecutive seq_puts calls
  scsi: replace seq_printf with seq_puts
  aha152x: replace seq_printf with seq_puts
  advansys: replace seq_printf with seq_puts
  scsi: remove SPRINTF macro
  sg: remove an unused variable
  hpsa: Use local workqueues instead of system workqueues
  hpsa: add in P840ar controller model name
  hpsa: add in gen9 controller model names
  hpsa: detect and report failures changing controller transport modes
  hpsa: shorten the wait for the CISS doorbell mode change ack
  hpsa: refactor duplicated scan completion code into a new routine
  hpsa: move SG descriptor set-up out of hpsa_scatter_gather()
  hpsa: do not use function pointers in fast path command submission
  hpsa: print CDBs instead of kernel virtual addresses for uncommon errors
  hpsa: do not use a void pointer for scsi_cmd field of struct CommandList
  hpsa: return failed from device reset/abort handlers
  hpsa: check for ctlr lockup after command allocation in main io path
  ...
</content>
</entry>
<entry>
<title>phy: qcom-ufs: add support for 20nm phy</title>
<updated>2015-01-20T18:43:25Z</updated>
<author>
<name>Yaniv Gardi</name>
<email>ygardi@codeaurora.org</email>
</author>
<published>2015-01-15T14:32:36Z</published>
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<id>urn:sha1:39e794bff718188cfb9ace2032cbe4fd86048dc6</id>
<content type='text'>
This change adds a support for a 20nm qcom-ufs phy that is required in
platforms that use ufs-qcom controller.

Signed-off-by: Yaniv Gardi &lt;ygardi@codeaurora.org&gt;
Reviewed-by: Dov Levenglick &lt;dovl@codeaurora.org&gt;
Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
</content>
</entry>
<entry>
<title>phy: phy-ti-pipe3: fix inconsistent enumeration of PCIe gen2 cards</title>
<updated>2014-12-23T10:14:32Z</updated>
<author>
<name>Vignesh R</name>
<email>vigneshr@ti.com</email>
</author>
<published>2014-12-16T09:22:50Z</published>
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<id>urn:sha1:0bc09f9cdc589e0b54724096138996a00b19babb</id>
<content type='text'>
Prior to DRA74x silicon rev 1.1, pcie_pcs register bits 8-15 and bits 16-23
were used to configure RC delay count for phy1 and phy2 respectively.
phyid was used as index to distinguish the phys and to configure the delay
values appropriately.

As of DRA74x silicon rev 1.1, pcie_pcs register definition has changed.
Bits 16-23 are used to configure delay values for *both* phy1 and phy2.

Hence phyid is no longer required.

So, drop id field from ti_pipe3 structure and its subsequent references
for configuring pcie_pcs register.

Also, pcie_pcs register now needs to be configured with delay value of 0x96
at bit positions 16-23. See register description of CTRL_CORE_PCIE_PCS in
ARM572x TRM, SPRUHZ6, October 2014, section 18.5.2.2, table 18-1804.

This is needed to ensure Gen2 cards are enumerated consistently.

DRA72x silicon behaves same way as DRA74x rev 1.1 as far as this functionality
is considered.

Test results on DRA74x and DRA72x EVMs:

Before patch
------------
DRA74x ES 1.0: Gen1 cards work, Gen2 cards do not work (expected result due to
silicon errata)
DRA74x ES 1.1: Gen1 cards work, Gen2 cards do not work sometimes due to incorrect
programming of register

DRA72x: Gen1 cards work, Gen2 cards do not work sometimes due to incorrect
programming of register

After patch
-----------
DRA74x ES 1.0: Gen1 cards work, Gen2 cards do not work (expected result due to
silicon errata)
DRA74x ES 1.1: Gen1 cards work, Gen2 cards work consistently.

DRA72x: Gen1 and Gen2 cards enumerate consistently.

Signed-off-by: Vignesh R &lt;vigneshr@ti.com&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>phy: remove the old lookup method</title>
<updated>2014-11-22T08:28:39Z</updated>
<author>
<name>Heikki Krogerus</name>
<email>heikki.krogerus@linux.intel.com</email>
</author>
<published>2014-11-19T15:28:21Z</published>
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<id>urn:sha1:dbc98635e0d42f0e62ea92813df1e0e4c90f8375</id>
<content type='text'>
The users of the old method are now converted to the new one.

Signed-off-by: Heikki Krogerus &lt;heikki.krogerus@linux.intel.com&gt;
[ kishon@ti.com : made phy-berlin-usb.c and phy-miphy28lp.c to use the updated
		  devm_phy_create API.]
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>phy: improved lookup method</title>
<updated>2014-11-21T14:18:50Z</updated>
<author>
<name>Heikki Krogerus</name>
<email>heikki.krogerus@linux.intel.com</email>
</author>
<published>2014-11-19T15:28:18Z</published>
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<id>urn:sha1:b7bc15b98e843926d01eb03b9c0e196d8ddbadeb</id>
<content type='text'>
Separates registration of the phy and the lookup. The method
is copied from clkdev.c,

Signed-off-by: Heikki Krogerus &lt;heikki.krogerus@linux.intel.com&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>phy: safer to_phy() macro</title>
<updated>2014-11-21T14:18:50Z</updated>
<author>
<name>Heikki Krogerus</name>
<email>heikki.krogerus@linux.intel.com</email>
</author>
<published>2014-11-19T15:28:17Z</published>
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<id>urn:sha1:d451057464a7ea2fe400e56c8a7e004c875f2a84</id>
<content type='text'>
This makes to_phy() macro work with other variable names
besides "dev".

Signed-off-by: Heikki Krogerus &lt;heikki.krogerus@linux.intel.com&gt;
Tested-by: Vivek Gautam &lt;gautam.vivek@samsung.com&gt;
Acked-by: Felipe Balbi &lt;balbi@ti.com&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>phy: core: Let node ptr of PHY point to PHY and not of PHY provider</title>
<updated>2014-07-22T07:16:11Z</updated>
<author>
<name>Kishon Vijay Abraham I</name>
<email>kishon@ti.com</email>
</author>
<published>2014-07-14T10:25:02Z</published>
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<id>urn:sha1:f0ed817638b59aa927f1f7e9564dd8796b18dc4f</id>
<content type='text'>
In case of multi-phy PHY providers, each PHY should be modeled as a sub
node of the PHY provider. Then each PHY will have a different node pointer
(node pointer of sub node) than that of PHY provider. Added this provision
in the PHY core.
Also fixed all drivers to use the updated API.

Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
Acked-by: Lee Jones &lt;lee.jones@linaro.org&gt;
</content>
</entry>
<entry>
<title>phy: core: Support regulator supply for PHY power</title>
<updated>2014-07-22T07:16:10Z</updated>
<author>
<name>Roger Quadros</name>
<email>rogerq@ti.com</email>
</author>
<published>2014-07-04T09:55:45Z</published>
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<id>urn:sha1:3be88125d85df587085b0be0a5c0e9953eb5ed6b</id>
<content type='text'>
Some PHYs can be powered by an external power regulator.
e.g. USB_HS PHY on DRA7 SoC. Make the PHY core support a
power regulator.

Signed-off-by: Roger Quadros &lt;rogerq@ti.com&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>phy: pipe3: insert delay to enumerate in GEN2 mode</title>
<updated>2014-07-22T07:16:10Z</updated>
<author>
<name>Kishon Vijay Abraham I</name>
<email>kishon@ti.com</email>
</author>
<published>2014-06-25T17:52:57Z</published>
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<id>urn:sha1:f0e2cf7b912522c9c7146d9d6e99d1b0ea5c97c6</id>
<content type='text'>
8-bit delay value (0xF1) is required for GEN2 devices to be enumerated
consistently. Added an API to be called from PHY drivers to set this delay
value and called it from PIPE3 driver to set the delay value.

Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
Reviewed-by: Roger Quadros &lt;rogerq@ti.com&gt;
</content>
</entry>
<entry>
<title>phy: core: make NULL a valid phy reference if !CONFIG_GENERIC_PHY</title>
<updated>2014-04-24T19:53:38Z</updated>
<author>
<name>Grygorii Strashko</name>
<email>grygorii.strashko@ti.com</email>
</author>
<published>2014-04-19T03:21:44Z</published>
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<id>urn:sha1:2b97789fa289d531e767d994a77e34ec58f328c4</id>
<content type='text'>
This fixes a regression on Keystone 2 platforms caused by patch
57303488cd37da58263e842de134dc65f7c626d5
"usb: dwc3: adapt dwc3 core to use Generic PHY Framework" which adds
optional support of generic phy in DWC3 core.

On Keystone 2 platforms the USB is not working now because
CONFIG_GENERIC_PHY isn't set and, as result, Generic PHY APIs stubs
return -ENOSYS always. The log shows:
 dwc3 2690000.dwc3: failed to initialize core
 dwc3: probe of 2690000.dwc3 failed with error -38

Hence, fix it by making NULL a valid phy reference in Generic PHY
APIs stubs in the same way as it was done by the patch
04c2facad8fee66c981a51852806d8923336f362 "drivers: phy: Make NULL
a valid phy reference".

Acked-by: Felipe Balbi &lt;balbi@ti.com&gt;
Acked-by: Santosh Shilimkar &lt;santosh.shilimkar@ti.com&gt;
Signed-off-by: Grygorii Strashko &lt;grygorii.strashko@ti.com&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
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