<feed xmlns='http://www.w3.org/2005/Atom'>
<title>user/sven/linux.git/include/linux/platform_data/edma.h, branch v4.4.25</title>
<subtitle>Linux Kernel
</subtitle>
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<updated>2015-12-10T03:01:10Z</updated>
<entry>
<title>dmaengine: edma: DT: Change memcpy channel array from 16bit to 32bit type</title>
<updated>2015-12-10T03:01:10Z</updated>
<author>
<name>Peter Ujfalusi</name>
<email>peter.ujfalusi@ti.com</email>
</author>
<published>2015-12-09T08:18:10Z</published>
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<id>urn:sha1:ecb7deceff2a51d3be50518969bc06411f485a62</id>
<content type='text'>
This change makes the DT file to be easier to read since the memcpy
channels array does not need the '/bits/ 16' to be specified, which might
confuse some people.

Signed-off-by: Peter Ujfalusi &lt;peter.ujfalusi@ti.com&gt;
Acked-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Acked-by: Tony Lindgren &lt;tony@atomide.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
<entry>
<title>dmaengine: edma: New device tree binding</title>
<updated>2015-10-27T01:22:45Z</updated>
<author>
<name>Peter Ujfalusi</name>
<email>peter.ujfalusi@ti.com</email>
</author>
<published>2015-10-16T07:18:10Z</published>
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<id>urn:sha1:1be5336bc7ba050ee07d352643bf4c01c513553c</id>
<content type='text'>
With the old binding and driver architecture we had many issues:
No way to assign eDMA channels to event queues, thus not able to tune the
system by moving specific DMA channels to low/high priority servicing. We
moved the cyclic channels to high priority within the code, but that was
just a workaround to this issue.
Memcopy was fundamentally broken: even if the driver scanned the DT/devices
in the booted system for direct DMA users (which is not effective when the
events are going through a crossbar) and created a map of 'used' channels,
this information was not really usable. Since via dmaengien API the eDMA
driver will be called with _some_ channel number, we would try to request
this channel when any channel is requested for memcpy. By luck we got
channel which is not used by any device most of the time so things worked,
but if a device would have been using the given channel, but not requested
it, the memcpy channel would have been waiting for HW event.
The old code had the am33xx/am43xx DMA event router handling embedded. This
should have been done in a separate driver since it is not part of the
actual eDMA IP.
There were no way to 'lock' PaRAM slots to be used by the DSP for example
when booting with DT.
In DT boot the edma node used more than one hwmod which is not a good
practice and the kernel prints warning because of this.

With the new bindings and the changes in the driver we can:
- No regression with Legacy binding and non DT boot
- DMA channels can be assigned to any TC (to set priority)
- PaRAM slots can be reserved for other cores to use
- Dynamic power management for CC and TCs, if only TC0 is used all other TC
  can be powered down for example

Signed-off-by: Peter Ujfalusi &lt;peter.ujfalusi@ti.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
<entry>
<title>ARM/dmaengine: edma: Merge the two drivers under drivers/dma/</title>
<updated>2015-10-14T14:27:11Z</updated>
<author>
<name>Peter Ujfalusi</name>
<email>peter.ujfalusi@ti.com</email>
</author>
<published>2015-10-14T11:42:53Z</published>
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<id>urn:sha1:2b6b3b7420190888793c49e97276e1e73bd7eaed</id>
<content type='text'>
Move the code out from arch/arm/common and merge it inside of the dmaengine
driver.
This change is done with as minimal (if eny) functional change to the code
as possible to avoid introducing regression.

Signed-off-by: Peter Ujfalusi &lt;peter.ujfalusi@ti.com&gt;
Acked-by: Tony Lindgren &lt;tony@atomide.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
<entry>
<title>ARM/dmaengine: edma: Public API to use private struct pointer</title>
<updated>2015-10-14T14:27:11Z</updated>
<author>
<name>Peter Ujfalusi</name>
<email>peter.ujfalusi@ti.com</email>
</author>
<published>2015-10-14T11:42:49Z</published>
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<id>urn:sha1:ca304fa9bb762f091e851d48de43f623c975d47a</id>
<content type='text'>
Instead of relying on indexes pointing to edma private date in the global
pointer array, pass the private data pointer via the public API.

Signed-off-by: Peter Ujfalusi &lt;peter.ujfalusi@ti.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
<entry>
<title>ARM: common: edma: Remove unused functions</title>
<updated>2015-10-14T14:25:34Z</updated>
<author>
<name>Peter Ujfalusi</name>
<email>peter.ujfalusi@ti.com</email>
</author>
<published>2015-10-14T11:42:44Z</published>
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<id>urn:sha1:d28c2b36d6027702585ca93773b3edd6e5f1a5bd</id>
<content type='text'>
We no longer have users for these functions so they can be removed.
Remove also unused enums from the header file.

Signed-off-by: Peter Ujfalusi &lt;peter.ujfalusi@ti.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
<entry>
<title>ARM: edma: Add edma_assign_channel_eventq() to move channel to a give queue</title>
<updated>2014-07-28T11:33:13Z</updated>
<author>
<name>Peter Ujfalusi</name>
<email>peter.ujfalusi@ti.com</email>
</author>
<published>2014-07-08T10:46:37Z</published>
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<id>urn:sha1:eb3fe7def66511120766c8fc05ee9631cce7fe6f</id>
<content type='text'>
In some cases it is desired to move a channel to a specific event queue.
Such a use case is audio, where it is preferred that it is served with
highest priority compared to other DMA clients.

Signed-off-by: Peter Ujfalusi &lt;peter.ujfalusi@ti.com&gt;
Acked-by: Sekhar Nori &lt;nsekhar@ti.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
<entry>
<title>ARM: edma: Remove redundant/unused parameters from edma_soc_info</title>
<updated>2014-05-22T09:25:25Z</updated>
<author>
<name>Peter Ujfalusi</name>
<email>peter.ujfalusi@ti.com</email>
</author>
<published>2014-05-16T12:17:20Z</published>
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<id>urn:sha1:903ed4913c7fe78d2746445564634264291c7493</id>
<content type='text'>
The following parameters are no longer needed by the edma driver since the
information can be obtained from the IP's CCCFG register:
n_channel, n_region, n_slot and n_tc.
Remove the n_cc as well since in this context it has no meaning. We have
separate edma_soc_info struct/eDMA3_CC instance so this member does not
make any sense (and the driver no longer uses it).

Signed-off-by: Peter Ujfalusi &lt;peter.ujfalusi@ti.com&gt;
Signed-off-by: Sekhar Nori &lt;nsekhar@ti.com&gt;
</content>
</entry>
<entry>
<title>ARM: edma: Remove queue_tc_mapping data from edma_soc_info</title>
<updated>2014-05-22T08:56:27Z</updated>
<author>
<name>Peter Ujfalusi</name>
<email>peter.ujfalusi@ti.com</email>
</author>
<published>2014-05-16T12:17:12Z</published>
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<id>urn:sha1:db885bf82883f9743efe09d91775c579c0ed6842</id>
<content type='text'>
It is no longer in use by the driver or board files.

Signed-off-by: Peter Ujfalusi &lt;peter.ujfalusi@ti.com&gt;
Signed-off-by: Sekhar Nori &lt;nsekhar@ti.com&gt;
</content>
</entry>
<entry>
<title>dmaengine: edma: Make reading the position of active channels work</title>
<updated>2014-04-30T05:04:39Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2014-04-28T10:49:43Z</published>
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<id>urn:sha1:cdae05a0f0f7d15837dfd6f4200e8caea03c9cbf</id>
<content type='text'>
As Joel pointed out, edma_read_position() uses memcpy_fromio() to read
the parameter ram. That's not synchronized with the internal update as
it does a byte by byte copy. We need to do a 32bit read to get a
consistent value.

Further reading destination and source is pointless. In DEV_TO_MEM
transfers we are only interested in the destination, in MEM_TO_DEV we
care about the source. In MEM_TO_MEM it really does not matter which
one you read.

Simple solution: Remove the pointers, select dest/source via a bool
and return the read value.

Remove the export of this function while at it. The only potential
user is the dmaengine and that's always builtin.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Acked-by: Sekhar Nori &lt;nsekhar@ti.com&gt;
Signed-off-by: Joel Fernandes &lt;joelf@ti.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
<entry>
<title>platform_data: edma: Be precise with the paRAM struct</title>
<updated>2014-04-22T16:04:49Z</updated>
<author>
<name>Peter Ujfalusi</name>
<email>peter.ujfalusi@ti.com</email>
</author>
<published>2014-04-14T11:41:56Z</published>
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<id>urn:sha1:8df4053f0532df8fe47d0434af51676b0fa65491</id>
<content type='text'>
The edmacc_param struct should follow the layout of the paRAM area in the
HW. Be explicit on the size of the fields (u32) and also mark the struct
as packed to avoid any padding on non 32bit architectures.

Signed-off-by: Peter Ujfalusi &lt;peter.ujfalusi@ti.com&gt;
Acked-by: Joel Fernandes &lt;joelf@ti.com&gt;
Reviewed-and-Tested-by: Joel Fernandes &lt;joelf@ti.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
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