user/sven/linux.git/include/linux/pxa2xx_ssp.h, branch v5.7

spi: pxa2xx: No need to keep pointer to platform device

2019-10-18T17:24:50Z

There is no need to keep a pointer to the platform device. Currently there are no users of it directly, and if there will be in the future we may restore it from pointer to the struct device. Convert all users at the same time. Cc: Russell King Cc: Jaroslav Kysela Cc: Takashi Iwai Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20191018105429.82782-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

2019-06-19T15:09:55Z

Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Enrico Weigelt Reviewed-by: Kate Stewart Reviewed-by: Allison Randal Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman

spi: pxa2xx: Add devicetree support

2018-10-11T14:28:04Z

The MMP2 platform, that uses device tree, has this controller. Let's add devicetree alongside platform & PCI. Signed-off-by: Lubomir Rintel Signed-off-by: Mark Brown

spi: pxa2xx: Use an enum for type

2018-10-11T14:28:03Z

That seems to be the correct type. Signed-off-by: Lubomir Rintel Signed-off-by: Mark Brown

ASoC: pxa-ssp: remove .set_pll() and .set_clkdiv() callbacks

2018-07-02T10:01:21Z

The .set_pll() and .set_clkdiv() callbacks are considered legacy and should not be used anymore. In order to support PXA boards on DT platforms, remove them and let the code figure out the correct dividers and PLL base frequencies itself. Signed-off-by: Daniel Mack Signed-off-by: Mark Brown

ARM: pxa: change SSP DMA channels allocation

2018-06-18T19:32:41Z

Now the dma_slave_map is available for PXA architecture, switch the SSP device to it. This specifically means that : - for platform data based machines, the DMA requestor channels are extracted from the slave map, where pxa-ssp-dai. is a 1-1 match to ssp., and the channels are either "rx" or "tx". - for device tree platforms, the dma node should be hooked into the pxa2xx-ac97 or pxa-ssp-dai node. Signed-off-by: Robert Jarzmik Acked-by: Daniel Mack

spi: pxa2xx: Add support for Intel Cannonlake

2017-06-06T19:01:15Z

Intel Cannonlake LPSS SPI has up to four chip selects per port like in Broxton and is clocked like Sunrisepoint and Kaby Lake. Add a new type LPSS_CNL_SSP and configuration that enable runtime chip select detection and use the same FIFO thresholds than in Sunrisepoint. Patch adds support for both Cannonlake SoC and PCH. Signed-off-by: Jarkko Nikula Signed-off-by: Mark Brown

spi: pxa2xx: fix indentation of the comments in header

2017-01-04T18:36:41Z

Just for sake of readability fix the indentation of the comments in pxa2xx_ssp.h header file. Signed-off-by: Andy Shevchenko Signed-off-by: Mark Brown

spi: pxa2xx: Default thresholds to PXA configuration

2016-09-12T19:01:43Z

Most of the devices in the supported list have PXA configuration of FIFO. In particularly Intel Medfield and Merrifield have bigger FIFO, than it's defined for CE4100. Split CE4100 in the similar way how it was done for Intel Quark, i.e. prefix definitions by CE4100 and append necessary pieces of code to switch case conditions. We are on safe side since those bits are ignored on all LPSS IPs. Signed-off-by: Andy Shevchenko Reviewed-by: Jarkko Nikula Signed-off-by: Mark Brown

spi: pxa2xx: Add support for both chip selects on Intel Braswell

2016-02-09T19:01:11Z

Intel Braswell LPSS SPI controller actually has two chip selects and there is no capabilities register where this could be found out. These two chip selects are controlled by bits which are in slightly differrent location than Broxton has. Braswell Windows driver also starts chip select (ACPI DeviceSelection) numbering from 1 so translate it to be suitable for Linux as well. Signed-off-by: Mika Westerberg Reviewed-by: Jarkko Nikula Reviewed-by: Andy Shevchenko Signed-off-by: Mark Brown