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<title>user/sven/linux.git/include/linux/qed, branch v5.6.10</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v5.6.10</id>
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<updated>2020-05-02T06:51:05Z</updated>
<entry>
<title>qed: Fix use after free in qed_chain_free</title>
<updated>2020-05-02T06:51:05Z</updated>
<author>
<name>Yuval Basson</name>
<email>ybason@marvell.com</email>
</author>
<published>2020-03-29T17:32:49Z</published>
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<id>urn:sha1:0f054066f8a5dff2ddca545295014412a4d0f484</id>
<content type='text'>
commit 8063f761cd7c17fc1d0018728936e0c33a25388a upstream.

The qed_chain data structure was modified in
commit 1a4a69751f4d ("qed: Chain support for external PBL") to support
receiving an external pbl (due to iWARP FW requirements).
The pages pointed to by the pbl are allocated in qed_chain_alloc
and their virtual address are stored in an virtual addresses array to
enable accessing and freeing the data. The physical addresses however
weren't stored and were accessed directly from the external-pbl
during free.

Destroy-qp flow, leads to freeing the external pbl before the chain is
freed, when the chain is freed it tries accessing the already freed
external pbl, leading to a use-after-free. Therefore we need to store
the physical addresses in additional to the virtual addresses in a
new data structure.

Fixes: 1a4a69751f4d ("qed: Chain support for external PBL")
Signed-off-by: Michal Kalderon &lt;mkalderon@marvell.com&gt;
Signed-off-by: Yuval Bason &lt;ybason@marvell.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>qed: FW 8.42.2.0 debug features</title>
<updated>2020-01-27T13:35:32Z</updated>
<author>
<name>Michal Kalderon</name>
<email>michal.kalderon@marvell.com</email>
</author>
<published>2020-01-27T13:26:19Z</published>
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<id>urn:sha1:2d22bc8354b15abe413dff76cfe0f7aeb88ef9aa</id>
<content type='text'>
Add to debug dump more information on the platform it was collected
from (pci func, path id).
Provide human readable reg fifo erros.

Removed static debug arrays from HSI Functions, and move them to
the hwfn.

Some structures were slightly changed (removing reserved chip id
for example) which lead to many long initializations being modified
with one parameter less during initialization. This leads to
some long diffs that don't really change anything.

Signed-off-by: Ariel Elior &lt;ariel.elior@marvell.com&gt;
Signed-off-by: Michal Kalderon &lt;michal.kalderon@marvell.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>qed: Debug feature: ilt and mdump</title>
<updated>2020-01-27T13:35:32Z</updated>
<author>
<name>Michal Kalderon</name>
<email>michal.kalderon@marvell.com</email>
</author>
<published>2020-01-27T13:26:17Z</published>
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<id>urn:sha1:8a52bbab39c9791480cbae86c69ad0d47f62972e</id>
<content type='text'>
Part of the FW drop includes new debug capabilities implemented in the
qed_debug file. This patch dumps additional information during ethtool -d
for better debugging. The data dumped is the ilt (internal logical table)
and information gathered by the management firmware incase there was a
crash and driver was not able to extract the information (mdump).

Signed-off-by: Ariel Elior &lt;ariel.elior@marvell.com&gt;
Signed-off-by: Michal Kalderon &lt;michal.kalderon@marvell.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>qed: FW 8.42.2.0 HSI changes</title>
<updated>2020-01-27T13:35:32Z</updated>
<author>
<name>Michal Kalderon</name>
<email>michal.kalderon@marvell.com</email>
</author>
<published>2020-01-27T13:26:15Z</published>
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<id>urn:sha1:0500a70d6e071040ffdaadebb966986afa83c5e9</id>
<content type='text'>
This patch contains several HSI changes. The changes are part of
features like RDMA VF and OVS, the patch also contains a fix to
how the init code determines if the dmae is ready to be used.

Signed-off-by: Ariel Elior &lt;ariel.elior@marvell.com&gt;
Signed-off-by: Michal Kalderon &lt;michal.kalderon@marvell.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>qed: FW 8.42.2.0 iscsi/fcoe changes</title>
<updated>2020-01-27T13:35:32Z</updated>
<author>
<name>Michal Kalderon</name>
<email>michal.kalderon@marvell.com</email>
</author>
<published>2020-01-27T13:26:14Z</published>
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<id>urn:sha1:6459d93619b5bc21f775e7eb12bc4d051743d7aa</id>
<content type='text'>
- Remove struct iscsi_slow_path_hdr and field fw_cid from several structs
- Remove struct iscsi_spe_func_dstry
- Remove fields pbe_page_size_log and pbl_page_size_log from struct
  iscsi_conn_offload_param

Signed-off-by: Manish Rangankar &lt;manish.rangankar@marvell.com&gt;
Signed-off-by: Saurav Kashyap &lt;saurav.kashyap@marvell.com&gt;
Signed-off-by: Ariel Elior &lt;ariel.elior@marvell.com&gt;
Signed-off-by: Michal Kalderon &lt;michal.kalderon@marvell.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>qed: Add abstraction for different hsi values per chip</title>
<updated>2020-01-27T13:35:32Z</updated>
<author>
<name>Michal Kalderon</name>
<email>michal.kalderon@marvell.com</email>
</author>
<published>2020-01-27T13:26:13Z</published>
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<id>urn:sha1:1392d19ff1d6ddd370cefa73b552a0262f9c35ea</id>
<content type='text'>
The number of BTB blocks was modified to be different between the two chip
flavors supported (BB/K2) as a result, this lead to a re-write of selecting
the default hsi value based on the chip.
This patch creates a lookup table for hsi values per chip rather than
ask again and again for every value.

Signed-off-by: Ariel Elior &lt;ariel.elior@marvell.com&gt;
Signed-off-by: Michal Kalderon &lt;michal.kalderon@marvell.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>qed: FW 8.42.2.0 Additional ll2 type</title>
<updated>2020-01-27T13:35:32Z</updated>
<author>
<name>Michal Kalderon</name>
<email>michal.kalderon@marvell.com</email>
</author>
<published>2020-01-27T13:26:12Z</published>
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<id>urn:sha1:997af5df230e3288ec1f5b332955f9be643e450b</id>
<content type='text'>
LL2 queues were a limited resource due to FW constraints.
This FW introduced a new resource which is a context based ll2 queue
(memory on host). The additional ll2 queues are required for RDMA SRIOV.
The code refers to the previous ll2 queues as ram-based or legacy, and the
new queues as ctx-based.
This change decreased the "legacy" ram-based queues therefore the first ll2
queue used for iWARP was converted to the ctx-based ll2 queue.
This feature also exposed a bug in the DIRECT_REG_WR64 macro implementation
which didn't have an effect in other use cases.

Signed-off-by: Ariel Elior &lt;ariel.elior@marvell.com&gt;
Signed-off-by: Michal Kalderon &lt;michal.kalderon@marvell.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>qed: FW 8.42.2.0 Internal ram offsets modifications</title>
<updated>2020-01-27T13:35:32Z</updated>
<author>
<name>Michal Kalderon</name>
<email>michal.kalderon@marvell.com</email>
</author>
<published>2020-01-27T13:26:07Z</published>
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<id>urn:sha1:2924e0699963b839f88f8c4e855929ea49185870</id>
<content type='text'>
IRO stands for internal RAM offsets. Updating the FW binary produces
different iro offsets. This file contains the different values,
and a new representation of the values.
Update the FW version

Signed-off-by: Ariel Elior &lt;ariel.elior@marvell.com&gt;
Signed-off-by: Michal Kalderon &lt;michal.kalderon@marvell.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma</title>
<updated>2019-09-21T17:26:24Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2019-09-21T17:26:24Z</published>
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<id>urn:sha1:018c6837f3e63b45163d55a1668d9f8e6fdecf6e</id>
<content type='text'>
Pull RDMA subsystem updates from Jason Gunthorpe:
 "This cycle mainly saw lots of bug fixes and clean up code across the
  core code and several drivers, few new functional changes were made.

   - Many cleanup and bug fixes for hns

   - Various small bug fixes and cleanups in hfi1, mlx5, usnic, qed,
     bnxt_re, efa

   - Share the query_port code between all the iWarp drivers

   - General rework and cleanup of the ODP MR umem code to fit better
     with the mmu notifier get/put scheme

   - Support rdma netlink in non init_net name spaces

   - mlx5 support for XRC devx and DC ODP"

* tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma: (99 commits)
  RDMA: Fix double-free in srq creation error flow
  RDMA/efa: Fix incorrect error print
  IB/mlx5: Free mpi in mp_slave mode
  IB/mlx5: Use the original address for the page during free_pages
  RDMA/bnxt_re: Fix spelling mistake "missin_resp" -&gt; "missing_resp"
  RDMA/hns: Package operations of rq inline buffer into separate functions
  RDMA/hns: Optimize cmd init and mode selection for hip08
  IB/hfi1: Define variables as unsigned long to fix KASAN warning
  IB/{rdmavt, hfi1, qib}: Add a counter for credit waits
  IB/hfi1: Add traces for TID RDMA READ
  RDMA/siw: Relax from kmap_atomic() use in TX path
  IB/iser: Support up to 16MB data transfer in a single command
  RDMA/siw: Fix page address mapping in TX path
  RDMA: Fix goto target to release the allocated memory
  RDMA/usnic: Avoid overly large buffers on stack
  RDMA/odp: Add missing cast for 32 bit
  RDMA/hns: Use devm_platform_ioremap_resource() to simplify code
  Documentation/infiniband: update name of some functions
  RDMA/cma: Fix false error message
  RDMA/hns: Fix wrong assignment of qp_access_flags
  ...
</content>
</entry>
<entry>
<title>qed*: Fix size of config attribute dump.</title>
<updated>2019-09-11T14:15:23Z</updated>
<author>
<name>Sudarsana Reddy Kalluru</name>
<email>skalluru@marvell.com</email>
</author>
<published>2019-09-11T11:42:50Z</published>
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<id>urn:sha1:9e54ba7c3752f27456ca691acc3f154e2597478c</id>
<content type='text'>
Driver currently returns max-buf-size as size of the config attribute.
This patch incorporates changes to read this value from MFW (if available)
and provide it to the user. Also did a trivial clean up in this path.

Fixes: d44a3ced7023 ("qede: Add support for reading the config id attributes.")
Signed-off-by: Sudarsana Reddy Kalluru &lt;skalluru@marvell.com&gt;
Signed-off-by: Ariel Elior &lt;aelior@marvell.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
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