<feed xmlns='http://www.w3.org/2005/Atom'>
<title>user/sven/linux.git/include/linux/soc/qcom, branch v5.15.76</title>
<subtitle>Linux Kernel
</subtitle>
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<updated>2022-04-20T07:34:04Z</updated>
<entry>
<title>soc: qcom: aoss: Expose send for generic usecase</title>
<updated>2022-04-20T07:34:04Z</updated>
<author>
<name>Deepak Kumar Singh</name>
<email>deesin@codeaurora.org</email>
</author>
<published>2021-08-31T14:30:27Z</published>
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<id>urn:sha1:7883df73fd594757f03e21da7598f4347da0441d</id>
<content type='text'>
commit 8c75d585b931ac874fbe4ee5a8f1811d20c2817f upstream.

Not all upcoming usecases will have an interface to allow the aoss
driver to hook onto. Expose the send api and create a get function to
enable drivers to send their own messages to aoss.

Signed-off-by: Chris Lew &lt;clew@codeaurora.org&gt;
Signed-off-by: Deepak Kumar Singh &lt;deesin@codeaurora.org&gt;
Reviewed-by: Stephen Boyd &lt;swboyd@chromium.org&gt;
Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Link: https://lore.kernel.org/r/1630420228-31075-2-git-send-email-deesin@codeaurora.org
Signed-off-by: Alex Elder &lt;elder@linaro.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: smd: Add support for SM6125 rpm clocks</title>
<updated>2021-08-06T01:27:56Z</updated>
<author>
<name>Martin Botka</name>
<email>martin.botka@somainline.org</email>
</author>
<published>2021-07-30T21:59:24Z</published>
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<id>urn:sha1:edeb2ca74716056b2be62925f21494d7af65150f</id>
<content type='text'>
Add rpm smd clocks, PMIC and bus clocks which are required on SM6125
for clients to vote on.

Signed-off-by: Martin Botka &lt;martin.botka@somainline.org&gt;
Link: https://lore.kernel.org/r/20210730215924.733350-2-martin.botka@somainline.org
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>soc: qcom: smem_state: Add devm_qcom_smem_state_get()</title>
<updated>2021-06-23T18:35:12Z</updated>
<author>
<name>Stephan Gerhold</name>
<email>stephan@gerhold.net</email>
</author>
<published>2021-06-18T11:15:54Z</published>
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<id>urn:sha1:61d1961adf4bd57d1b2c6d94d97323263c470cb2</id>
<content type='text'>
It is easy to forget to call qcom_smem_state_put() after
a qcom_smem_state_get(). Introduce a devm_qcom_smem_state_get()
helper function that automates this so that qcom_smem_state_put()
is automatically called when a device is removed.

Signed-off-by: Stephan Gerhold &lt;stephan@gerhold.net&gt;
Reviewed-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Link: https://lore.kernel.org/r/20210618111556.53416-1-stephan@gerhold.net
Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
</content>
</entry>
<entry>
<title>soc: qcom: address kernel-doc warnings</title>
<updated>2021-03-30T03:49:54Z</updated>
<author>
<name>Lukas Bulwahn</name>
<email>lukas.bulwahn@gmail.com</email>
</author>
<published>2021-03-27T06:56:42Z</published>
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<id>urn:sha1:8058dfa05ab765153f20020fc4ea3b296e391a00</id>
<content type='text'>
The command:

  find ./include/linux/soc/qcom/ | xargs ./scripts/kernel-doc -none

reports:

  ./include/linux/soc/qcom/qmi.h:26: warning: cannot understand function prototype: 'struct qmi_header '
  ./include/linux/soc/qcom/qmi.h:101: warning: cannot understand function prototype: 'struct qmi_response_type_v01 '
  ./include/linux/soc/qcom/irq.h:19: warning: expecting prototype for QCOM specific IRQ domain flags that distinguishes the handling of wakeup(). Prototype was for IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP() instead
  ./include/linux/soc/qcom/apr.h:126: warning: Function parameter or member '__apr_driver' not described in 'module_apr_driver'
  ./include/linux/soc/qcom/apr.h:126: warning: Excess function parameter '__aprbus_driver' description in 'module_apr_driver'
  ./include/linux/soc/qcom/llcc-qcom.h:43: warning: cannot understand function prototype: 'struct llcc_slice_desc '
  ./include/linux/soc/qcom/llcc-qcom.h:60: warning: cannot understand function prototype: 'struct llcc_edac_reg_data '
  ./include/linux/soc/qcom/llcc-qcom.h:86: warning: cannot understand function prototype: 'struct llcc_drv_data '

Address all those warnings by:
  - prefixing kernel-doc descriptions for structs with the keyword 'struct',
  - turning a kernel-doc comment that does not follow the kernel-doc syntax
  into a normal comment, and
  - correcting a parameter name in a kernel-doc comment.

Signed-off-by: Lukas Bulwahn &lt;lukas.bulwahn@gmail.com&gt;
Link: https://lore.kernel.org/r/20210327065642.11969-3-lukas.bulwahn@gmail.com
Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'arm-drivers-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc</title>
<updated>2021-02-21T02:42:28Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2021-02-21T02:42:28Z</published>
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<id>urn:sha1:e767b3530acbf651593e3d357fe1168a024d8061</id>
<content type='text'>
Pull ARM SoC driver updates from Arnd Bergmann:
 "Updates for SoC specific drivers include a few subsystems that have
  their own maintainers but send them through the soc tree:

  SCMI firmware:
   - add support for a completion interrupt

  Reset controllers:
   - new driver for BCM4908
   - new devm_reset_control_get_optional_exclusive_released() function

  Memory controllers:
   - Renesas RZ/G2 support
   - Tegra124 interconnect support
   - Allow more drivers to be loadable modules

  TEE/optee firmware:
   - minor code cleanup

  The other half of this is SoC specific drivers that do not belong into
  any other subsystem, most of them living in drivers/soc:

   - Allwinner/sunxi power management work
   - Allwinner H616 support

   - ASpeed AST2600 system identification support

   - AT91 SAMA7G5 SoC ID driver
   - AT91 SoC driver cleanups

   - Broadcom BCM4908 power management bus support

   - Marvell mbus cleanups

   - Mediatek MT8167 power domain support

   - Qualcomm socinfo driver support for PMIC
   - Qualcomm SoC identification for many more products

   - TI Keystone driver cleanups for PRUSS and elsewhere"

* tag 'arm-drivers-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (89 commits)
  soc: aspeed: socinfo: Add new systems
  soc: aspeed: snoop: Add clock control logic
  memory: tegra186-emc: Replace DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTE
  memory: samsung: exynos5422-dmc: Correct function names in kerneldoc
  memory: ti-emif-pm: Drop of_match_ptr from of_device_id table
  optee: simplify i2c access
  drivers: soc: atmel: fix type for same7
  tee: optee: remove need_resched() before cond_resched()
  soc: qcom: ocmem: don't return NULL in of_get_ocmem
  optee: sync OP-TEE headers
  tee: optee: fix 'physical' typos
  drivers: optee: use flexible-array member instead of zero-length array
  tee: fix some comment typos in header files
  soc: ti: k3-ringacc: Use of_device_get_match_data()
  soc: ti: pruss: Refactor the CFG sub-module init
  soc: mediatek: pm-domains: Don't print an error if child domain is deferred
  soc: mediatek: pm-domains: Add domain regulator supply
  dt-bindings: power: Add domain regulator supply
  soc: mediatek: cmdq: Remove cmdq_pkt_flush()
  soc: mediatek: pm-domains: Add support for mt8167
  ...
</content>
</entry>
<entry>
<title>soc: qcom: mdt_loader: define stubs for COMPILE_TEST</title>
<updated>2021-01-09T21:51:36Z</updated>
<author>
<name>Alex Elder</name>
<email>elder@linaro.org</email>
</author>
<published>2021-01-07T23:34:02Z</published>
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<id>urn:sha1:ce2ceb9b1cff777c7d8beb368eddc3b8e45381f6</id>
<content type='text'>
Define stub functions for the exposed MDT functions in case
QCOM_MDT_LOADER is not configured.  This allows users of these
functions to link correctly for COMPILE_TEST builds without
QCOM_SCM enabled.

Reviewed-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Signed-off-by: Alex Elder &lt;elder@linaro.org&gt;
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>soc: qcom: llcc-qcom: Add support for SM8250 SoC</title>
<updated>2020-12-28T18:15:14Z</updated>
<author>
<name>Manivannan Sadhasivam</name>
<email>manivannan.sadhasivam@linaro.org</email>
</author>
<published>2020-11-30T09:39:24Z</published>
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<id>urn:sha1:c4df37fe186de4df8895a7a4793f5221eda6e5ae</id>
<content type='text'>
SM8250 SoC uses LLCC IP version 2. In this version, the WRSC_EN register
needs to be written to enable the Write Sub Cache for each SCID. Hence,
use a dedicated "write_scid_en" member with predefined values and write
them for LLCC IP version 2.

Reviewed-by: Sai Prakash Ranjan &lt;saiprakash.ranjan@codeaurora.org&gt;
Signed-off-by: Manivannan Sadhasivam &lt;manivannan.sadhasivam@linaro.org&gt;
Link: https://lore.kernel.org/r/20201130093924.45057-5-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
</content>
</entry>
<entry>
<title>soc: qcom: llcc-qcom: Extract major hardware version</title>
<updated>2020-12-28T18:15:13Z</updated>
<author>
<name>Sai Prakash Ranjan</name>
<email>saiprakash.ranjan@codeaurora.org</email>
</author>
<published>2020-11-30T09:39:23Z</published>
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<id>urn:sha1:916c0c05521a52f13283ad3600793fc79516ff31</id>
<content type='text'>
The major hardware version of the LLCC IP is encoded in its
LLCC_COMMON_HW_INFO register. Extract the version and cache it in the
driver data so that it can be used to implement version specific
functionality like enabling Write sub cache for given SCID.

Signed-off-by: Sai Prakash Ranjan &lt;saiprakash.ranjan@codeaurora.org&gt;
[mani: splitted the version extract as a single patch and few cleanups]
Signed-off-by: Manivannan Sadhasivam &lt;manivannan.sadhasivam@linaro.org&gt;
Link: https://lore.kernel.org/r/20201130093924.45057-4-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
</content>
</entry>
<entry>
<title>soc: qcom: llcc: Add configuration data for SM8150</title>
<updated>2020-11-20T04:22:25Z</updated>
<author>
<name>Souradeep Chowdhury</name>
<email>schowdhu@codeaurora.org</email>
</author>
<published>2020-09-30T08:14:13Z</published>
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<id>urn:sha1:ded5ed04d85e299770dcb7e82c2127b8054a00c8</id>
<content type='text'>
Add LLCC configuration data for SM8150 SoC which controls
LLCC behaviour.

Signed-off-by: Souradeep Chowdhury &lt;schowdhu@codeaurora.org&gt;
Link: https://lore.kernel.org/r/957e3ae50c75720ef6227529d5ce3d4b457802e9.1601452132.git.schowdhu@codeaurora.org
Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
</content>
</entry>
<entry>
<title>regulator: qcom_smd: Add PM660/PM660L regulator support</title>
<updated>2020-10-01T20:25:25Z</updated>
<author>
<name>AngeloGioacchino Del Regno</name>
<email>kholk11@gmail.com</email>
</author>
<published>2020-09-26T12:55:47Z</published>
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<id>urn:sha1:6d849653b00f2336efcd371fe85a7eb31bb094e9</id>
<content type='text'>
The PM660 and PM660L are a very very common PMIC combo, found on
boards using the SDM630, SDM636, SDM660 (and SDA variants) SoC.

PM660 provides 6 SMPS and 19 LDOs (of which one is unaccesible),
while PM660L provides 5 SMPS (of which S3 and S4 are combined),
10 LDOs and a Buck-or-Boost (BoB) regulator.

The PM660L IC also provides other regulators that are very
specialized (for example, for the display) and will be managed
in the other appropriate drivers (for example, labibb).

Signed-off-by: AngeloGioacchino Del Regno &lt;kholk11@gmail.com&gt;
Link: https://lore.kernel.org/r/20200926125549.13191-6-kholk11@gmail.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
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