user/sven/linux.git/include/linux/soc, branch v4.19.221

Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

2018-08-23T20:44:43Z

Pull ARM 32-bit SoC platform updates from Olof Johansson: "Most of the SoC updates in this cycle are cleanups and moves to more modern infrastructure: - Davinci was moved to common clock framework - OMAP1-based Amstrad E3 "Superphone" saw a bunch of cleanups to the keyboard interface (bitbanged AT keyboard via GPIO). - Removal of some stale code for Renesas platforms - Power management improvements for i.MX6LL" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (112 commits) ARM: uniphier: select RESET_CONTROLLER arm64: uniphier: select RESET_CONTROLLER ARM: uniphier: remove empty Makefile ARM: exynos: Clear global variable on init error path ARM: exynos: Remove outdated maintainer information ARM: shmobile: Always enable ARCH_TIMER on SoCs with A7 and/or A15 ARM: shmobile: r8a7779: hide unused r8a7779_platform_cpu_kill soc: r9a06g032: don't build SMP files for non-SMP config ARM: shmobile: Add the R9A06G032 SMP enabler driver ARM: at91: pm: configure wakeup sources for ULP1 mode ARM: at91: pm: add PMC fast startup registers defines ARM: at91: pm: Add ULP1 mode support ARM: at91: pm: Use ULP0 naming instead of slow clock ARM: hisi: handle of_iomap and fix missing of_node_put ARM: hisi: check of_iomap and fix missing of_node_put ARM: hisi: fix error handling and missing of_node_put ARM: mx5: Set the DBGEN bit in ARM_GPC register ARM: imx51: Configure M4IF to avoid visual artifacts ARM: imx: call imx6sx_cpuidle_init() conditionally for 6sll ARM: imx: fix i.MX6SLL build ...

Merge tag 'rproc-v4.19' of git://github.com/andersson/remoteproc

2018-08-18T23:42:04Z

Pull remoteproc updates from Bjorn Andersson: "This adds support for pre-start and post-shutdown hooks for remoteproc subdevices, refactors the Qualcomm Hexagon support to allow reuse between several drivers, makes authentication in the MDT file loader optional, migrates a few format strings to use %pK and migrates the Davinci driver to use the reset framework" * tag 'rproc-v4.19' of git://github.com/andersson/remoteproc: remoteproc/davinci: use the reset framework remoteproc/davinci: Mark error recovery as disabled remoteproc: st_slim: replace "%p" with "%pK" remoteproc: replace "%p" with "%pK" remoteproc: qcom: fix Q6V5_WCSS dependencies remoteproc: Reset table_ptr in rproc_start() failure paths remoteproc: qcom: q6v5-pil: fix modem hang on SDM845 after axis2 clk unvote remoteproc: qcom q6v5: fix modular build remoteproc: Introduce prepare and unprepare for subdevices remoteproc: rename subdev probe and remove functions remoteproc: Make client initialize ops in rproc_subdev remoteproc: Make start and stop in subdev optional remoteproc: Rename subdev functions to start/stop remoteproc: qcom: Introduce Hexagon V5 based WCSS driver remoteproc: qcom: q6v5-pil: Use common q6v5 helpers remoteproc: qcom: adsp: Use common q6v5 helpers remoteproc: q6v5: Extract common resource handling remoteproc: qcom: mdt_loader: Make the firmware authentication optional

Merge tag 'pinctrl-v4.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2018-08-14T19:31:27Z

Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for v4.19: Core changes: - Augment pinctrl_generic_add_group() and pinmux_generic_add_function() to return the selector for the added group/function to the caller and augment (hopefully) all drivers to handle this New subdrivers: - Qualcomm PM8998 and PM8005 are supported in the SPMI pin control and GPIO driver - Intel Ice Lake PCH (platform controller hub) support - NXP (ex Freescale) i.MX8MQ support - Berlin AS370 support Improvements to drivers: - Support interrupts on the Ocelot pin controller - Add SPI pins to the Uniphier driver - Define a GPIO compatible per SoC in the Tegra driver - Push Tegra initialization down in the initlevels - Support external wakeup interrupts on the Exynos - Add generic clocks pins to the meson driver - Add USB and HSCIF pins for some Renesas PFC chips - Suspend/resume support in the armada-37xx - Interrupt support for the Actions Semiconductor S900 also known as "owl" - Correct the pin ordering in Cedarfork - Debugfs output for INTF in the mcp23s08 driver - Avoid divisions in context save/restore in pinctrl-single The rest is minor bug fixes or cleanups" * tag 'pinctrl-v4.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (69 commits) pinctrl: nomadik: silence uninitialized variable warning pinctrl: axp209: Fix NULL pointer dereference after allocation pinctrl: samsung: Remove duplicated "wakeup" in printk pinctrl: ocelot: add support for interrupt controller pinctrl: intel: Don't shadow error code of gpiochip_lock_as_irq() pinctrl: berlin: fix 'pctrl->functions' allocation in berlin_pinctrl_build_state gpio: tegra: Move driver registration to subsys_init level pinctrl: tegra: Move drivers registration to arch_init level pinctrl: baytrail: actually print the apparently misconfigured pin MAINTAINERS: Replace Heikki as maintainer of Intel pinctrl pinctrl: freescale: off by one in imx1_pinconf_group_dbg_show() pinctrl: uniphier: add spi pin-mux settings pinctrl: cannonlake: Fix community ordering for H variant pinctrl: tegra: define GPIO compatible node per SoC pinctrl: intel: Do pin translation when lock IRQ pinctrl: imx: off by one in imx_pinconf_group_dbg_show() pinctrl: mediatek: include chained_irq.h header pinctrl/amd: only handle irq if it is pending and unmasked pinctrl/amd: fix gpio irq level in debugfs pinctrl: stm32: add syscfg mask parameter ...

pinctrl: samsung: Write external wakeup interrupt mask

2018-07-24T19:56:41Z

The pinctrl driver defines an IRQ chip which handles external wakeup interrupts, therefore from logical point of view, it is the owner of external interrupt mask. The register controlling the mask belongs to Power Management Unit address space so it has to be accessed with PMU syscon regmap handle. This mask should be written to hardware during system suspend. Till now ARMv7 machine code was responsible for this which created a dependency between pin controller driver and arch/arm/mach code. Try to rework this dependency so the pinctrl driver will write external wakeup interrupt mask during late suspend. Impact on ARMv7 designs (S5Pv210 and Exynos) ============================================ This duplicates setting mask with existing machine code arch/arm/mach-exynos/suspend.c and arch/arm/mach-s5pv210/pm.c but it is not a problem - the wakeup mask register will be written twice. The machine code will be cleaned up later. The difference between implementation here and ARMv7 machine code (arch/arm/mach-*) is the time of writing the mask: 1. The machine code is writing the mask quite late during system suspend path, after offlining secondary CPUs and just before doing actual suspend. 2. The implementation in pinctrl driver uses late suspend ops, therefore it will write the mask much earlier. Hopefully late enough, after all drivers will enable or disable their interrupt wakeups (enable_irq_wake() etc). Impact on ARMv8 designs (Exynos5433 and Exynos7) ================================================ The Suspend to RAM was not supported and external wakeup interrupt mask was not written to HW. This change brings us one step closer to supporting Suspend to RAM. Signed-off-by: Krzysztof Kozlowski Cc: Tomasz Figa Cc: Sylwester Nawrocki Acked-by: Tomasz Figa Tested-by: Marek Szyprowski

ARM: exynos: Define EINT_WAKEUP_MASK registers for S5Pv210 and Exynos5433

2018-07-24T19:50:39Z

S5Pv210 and Exynos5433/Exynos7 have different address of EINT_WAKEUP_MASK register. Rename existing S5P_EINT_WAKEUP_MASK to avoid confusion and add new ones. Signed-off-by: Krzysztof Kozlowski Cc: Tomasz Figa Cc: Sylwester Nawrocki Acked-by: Tomasz Figa Tested-by: Marek Szyprowski

drivers: soc: Add LLCC driver

2018-07-21T18:31:35Z

LLCC (Last Level Cache Controller) provides additional cache memory in the system. LLCC is partitioned into multiple slices and each slice gets its own priority, size, ID and other config parameters. LLCC driver programs these parameters for each slice. Clients that are assigned to use LLCC need to get information such size & ID of the slice they get and activate or deactivate the slice as needed. LLCC driver provides API for the clients to perform these operations. Signed-off-by: Channagoud Kadabi Signed-off-by: Rishabh Bhatnagar Reviewed-by: Evan Green Reviewed-by: Rob Herring Reviewed-by: Bjorn Andersson Signed-off-by: Andy Gross

remoteproc: qcom: mdt_loader: Make the firmware authentication optional

2018-06-18T22:55:31Z

qcom_mdt_load function loads the mdt type firmware and initialises the secure memory as well. Make the initialisation only when requested by the caller, so that the function can be used by self-authenticating remoteproc as well. Acked-by: Andy Gross Signed-off-by: Sricharan R Signed-off-by: Bjorn Andersson

soc: renesas: rcar-sysc: Drop legacy handling

2018-06-18T10:00:29Z

Now the R-Car platform code no longer supports DTBs lacking a SYSC device node in DT, all legacy handling can be dropped from the R-Car SYSC driver: - Make rcar_sysc_ch private to the driver, - Make rcar_sysc_power_{down,up}() static (they have been replaced by rcar_sysc_power_{down,up}_cpu()), - Remove the legacy wrapper rcar_sysc_init(), and the check for double initialization (only the early_initcall is left). Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman

soc: renesas: rcar-sysc: Provide helpers to power up/down CPUs

2018-06-18T10:00:28Z

Provide helpers to control CPU power areas from platform code, taking just a CPU index. This will avoid having to pass full CPU power area parameter blocks, and thus duplicating information already provided by SoC-specific SYSC drivers. This will be used on R-Car H1 only. Later R-Car generations rely on APMU/RST for CPU power area control. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman

Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

2018-06-12T01:19:45Z

Pull ARM SoC late updates from Olof Johansson: "This is a branch with a few merge requests that either came in late, or took a while longer for us to review and merge than usual and thus cut it a bit close to the merge window. We stage them in a separate branch and if things look good, we still send them up -- and that's the case here. This is mostly DT additions for Renesas platforms, adding IP block descriptions for existing and new SoCs. There are also some driver updates for Qualcomm platforms for SMEM/QMI and GENI, which is their generalized serial protocol interface" * tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (186 commits) soc: qcom: smem: introduce qcom_smem_virt_to_phys() soc: qcom: qmi: fix a buffer sizing bug MAINTAINERS: Update pattern for qcom_scm soc: Unconditionally include qcom Makefile soc: qcom: smem: check sooner in qcom_smem_set_global_partition() soc: qcom: smem: fix qcom_smem_set_global_partition() soc: qcom: smem: fix off-by-one error in qcom_smem_alloc_private() soc: qcom: smem: byte swap values properly soc: qcom: smem: return proper type for cached entry functions soc: qcom: smem: fix first cache entry calculation soc: qcom: cmd-db: Make endian-agnostic drivers: qcom: add command DB driver arm64: dts: renesas: salvator-common: Add ADV7482 support ARM: dts: r8a7740: Add CEU1 ARM: dts: r8a7740: Add CEU0 arm64: dts: renesas: salvator-common: enable VIN arm64: dts: renesas: r8a77970: add VIN and CSI-2 nodes arm64: dts: renesas: r8a77965: add VIN and CSI-2 nodes arm64: dts: renesas: r8a7796: add VIN and CSI-2 nodes arm64: dts: renesas: r8a7795-es1: add CSI-2 node ...