user/sven/linux.git/include/linux/soc, branch v4.20.11

Merge tag 'qcom-drivers-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/drivers

2018-10-02T08:11:12Z

Qualcomm ARM Based Driver Updates for v4.20 * Refactor of SCM compatibles and clock requirements * SMEM cleanup * Add LLCC EDAC driver * Fixes for GENI clocks and macros * Fix includes for llcc-slice and smem * String overflow fixes for APR and wcnss_ctrl * Fixup for COMPILE_TEST of qcom driver Kconfigs * Cleanup of Kconfig depends of rpmh, smd_rpm, smsm, and smp2p * Add SCM dependencies to SPM and rmtfs-mem * tag 'qcom-drivers-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: (38 commits) soc: qcom: geni: geni_se_clk_freq_match() should always accept multiples soc: qcom: geni: Don't ignore clk_round_rate() errors in geni_se_clk_tbl_get() soc: qcom: geni: Make version macros simpler dt-bindings: firmware: scm: Add MSM8998 and SDM845 firmware: qcom: scm: Refactor clock handling dt-bindings: firmware: scm: Refactor compatibles and clocks soc: qcom: smem: a few last cleanups soc: qcom: smem: verify partition host ids match soc: qcom: smem: small change in global entry loop soc: qcom: smem: verify partition offset_free_uncached soc: qcom: smem: verify partition header size soc: qcom: smem: introduce qcom_smem_partition_header() soc: qcom: smem: require order of host ids to match soc: qcom: smem: verify both host ids in partition header soc: qcom: smem: small refactor in qcom_smem_enumerate_partitions() soc: qcom: smem: always ignore partitions with 0 offset or size soc: qcom: smem: initialize region struct only when successful soc: qcom: smem: rename variable in qcom_smem_get_global() drivers: qcom: rpmh-rsc: clear wait_for_compl after use soc: qcom: rmtfs-mem: Validate that scm is available ... Signed-off-by: Arnd Bergmann

drivers: edac: Add EDAC driver support for QCOM SoCs

2018-09-13T20:54:05Z

Add error reporting driver for Single Bit Errors (SBEs) and Double Bit Errors (DBEs). As of now, this driver supports error reporting for Last Level Cache Controller (LLCC) of Tag RAM and Data RAM. Interrupts are triggered when the errors happen in the cache, the driver handles those interrupts and dumps the syndrome registers. Signed-off-by: Channagoud Kadabi Signed-off-by: Venkata Narendra Kumar Gutta Co-developed-by: Venkata Narendra Kumar Gutta Acked-by: Borislav Petkov Signed-off-by: Andy Gross

soc: qcom: Add support to register LLCC EDAC driver

2018-09-13T20:53:58Z

Cache error reporting controller detects and reports single and double bit errors on Last Level Cache Controller (LLCC) cache. Add required support to register LLCC EDAC driver as platform driver, from LLCC driver. Signed-off-by: Venkata Narendra Kumar Gutta Reviewed-by: Evan Green Signed-off-by: Andy Gross

soc: qcom: Add broadcast base for Last Level Cache Controller (LLCC)

2018-09-13T20:53:51Z

Currently, broadcast base is set to end of the LLCC banks, which may not be correct always. As the number of banks may vary for each chipset and the broadcast base could be at a different address as well. This info depends on the chipset, so get the broadcast base info from the device tree (DT). Add broadcast base in LLCC driver and use this for broadcast writes. Signed-off-by: Venkata Narendra Kumar Gutta Reviewed-by: Evan Green Signed-off-by: Andy Gross

soc: amlogic: add meson-canvas driver

2018-09-13T04:38:45Z

Amlogic SoCs have a repository of 256 canvas which they use to describe pixel buffers. They contain metadata like width, height, block mode, endianness [..] Many IPs within those SoCs like vdec/vpu rely on those canvas to read/write pixels. Reviewed-by: Jerome Brunet Tested-by: Neil Armstrong Signed-off-by: Maxime Jourdan Signed-off-by: Kevin Hilman

Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

2018-08-23T20:44:43Z

Pull ARM 32-bit SoC platform updates from Olof Johansson: "Most of the SoC updates in this cycle are cleanups and moves to more modern infrastructure: - Davinci was moved to common clock framework - OMAP1-based Amstrad E3 "Superphone" saw a bunch of cleanups to the keyboard interface (bitbanged AT keyboard via GPIO). - Removal of some stale code for Renesas platforms - Power management improvements for i.MX6LL" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (112 commits) ARM: uniphier: select RESET_CONTROLLER arm64: uniphier: select RESET_CONTROLLER ARM: uniphier: remove empty Makefile ARM: exynos: Clear global variable on init error path ARM: exynos: Remove outdated maintainer information ARM: shmobile: Always enable ARCH_TIMER on SoCs with A7 and/or A15 ARM: shmobile: r8a7779: hide unused r8a7779_platform_cpu_kill soc: r9a06g032: don't build SMP files for non-SMP config ARM: shmobile: Add the R9A06G032 SMP enabler driver ARM: at91: pm: configure wakeup sources for ULP1 mode ARM: at91: pm: add PMC fast startup registers defines ARM: at91: pm: Add ULP1 mode support ARM: at91: pm: Use ULP0 naming instead of slow clock ARM: hisi: handle of_iomap and fix missing of_node_put ARM: hisi: check of_iomap and fix missing of_node_put ARM: hisi: fix error handling and missing of_node_put ARM: mx5: Set the DBGEN bit in ARM_GPC register ARM: imx51: Configure M4IF to avoid visual artifacts ARM: imx: call imx6sx_cpuidle_init() conditionally for 6sll ARM: imx: fix i.MX6SLL build ...

Merge tag 'rproc-v4.19' of git://github.com/andersson/remoteproc

2018-08-18T23:42:04Z

Pull remoteproc updates from Bjorn Andersson: "This adds support for pre-start and post-shutdown hooks for remoteproc subdevices, refactors the Qualcomm Hexagon support to allow reuse between several drivers, makes authentication in the MDT file loader optional, migrates a few format strings to use %pK and migrates the Davinci driver to use the reset framework" * tag 'rproc-v4.19' of git://github.com/andersson/remoteproc: remoteproc/davinci: use the reset framework remoteproc/davinci: Mark error recovery as disabled remoteproc: st_slim: replace "%p" with "%pK" remoteproc: replace "%p" with "%pK" remoteproc: qcom: fix Q6V5_WCSS dependencies remoteproc: Reset table_ptr in rproc_start() failure paths remoteproc: qcom: q6v5-pil: fix modem hang on SDM845 after axis2 clk unvote remoteproc: qcom q6v5: fix modular build remoteproc: Introduce prepare and unprepare for subdevices remoteproc: rename subdev probe and remove functions remoteproc: Make client initialize ops in rproc_subdev remoteproc: Make start and stop in subdev optional remoteproc: Rename subdev functions to start/stop remoteproc: qcom: Introduce Hexagon V5 based WCSS driver remoteproc: qcom: q6v5-pil: Use common q6v5 helpers remoteproc: qcom: adsp: Use common q6v5 helpers remoteproc: q6v5: Extract common resource handling remoteproc: qcom: mdt_loader: Make the firmware authentication optional

Merge tag 'pinctrl-v4.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2018-08-14T19:31:27Z

Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for v4.19: Core changes: - Augment pinctrl_generic_add_group() and pinmux_generic_add_function() to return the selector for the added group/function to the caller and augment (hopefully) all drivers to handle this New subdrivers: - Qualcomm PM8998 and PM8005 are supported in the SPMI pin control and GPIO driver - Intel Ice Lake PCH (platform controller hub) support - NXP (ex Freescale) i.MX8MQ support - Berlin AS370 support Improvements to drivers: - Support interrupts on the Ocelot pin controller - Add SPI pins to the Uniphier driver - Define a GPIO compatible per SoC in the Tegra driver - Push Tegra initialization down in the initlevels - Support external wakeup interrupts on the Exynos - Add generic clocks pins to the meson driver - Add USB and HSCIF pins for some Renesas PFC chips - Suspend/resume support in the armada-37xx - Interrupt support for the Actions Semiconductor S900 also known as "owl" - Correct the pin ordering in Cedarfork - Debugfs output for INTF in the mcp23s08 driver - Avoid divisions in context save/restore in pinctrl-single The rest is minor bug fixes or cleanups" * tag 'pinctrl-v4.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (69 commits) pinctrl: nomadik: silence uninitialized variable warning pinctrl: axp209: Fix NULL pointer dereference after allocation pinctrl: samsung: Remove duplicated "wakeup" in printk pinctrl: ocelot: add support for interrupt controller pinctrl: intel: Don't shadow error code of gpiochip_lock_as_irq() pinctrl: berlin: fix 'pctrl->functions' allocation in berlin_pinctrl_build_state gpio: tegra: Move driver registration to subsys_init level pinctrl: tegra: Move drivers registration to arch_init level pinctrl: baytrail: actually print the apparently misconfigured pin MAINTAINERS: Replace Heikki as maintainer of Intel pinctrl pinctrl: freescale: off by one in imx1_pinconf_group_dbg_show() pinctrl: uniphier: add spi pin-mux settings pinctrl: cannonlake: Fix community ordering for H variant pinctrl: tegra: define GPIO compatible node per SoC pinctrl: intel: Do pin translation when lock IRQ pinctrl: imx: off by one in imx_pinconf_group_dbg_show() pinctrl: mediatek: include chained_irq.h header pinctrl/amd: only handle irq if it is pending and unmasked pinctrl/amd: fix gpio irq level in debugfs pinctrl: stm32: add syscfg mask parameter ...

pinctrl: samsung: Write external wakeup interrupt mask

2018-07-24T19:56:41Z

The pinctrl driver defines an IRQ chip which handles external wakeup interrupts, therefore from logical point of view, it is the owner of external interrupt mask. The register controlling the mask belongs to Power Management Unit address space so it has to be accessed with PMU syscon regmap handle. This mask should be written to hardware during system suspend. Till now ARMv7 machine code was responsible for this which created a dependency between pin controller driver and arch/arm/mach code. Try to rework this dependency so the pinctrl driver will write external wakeup interrupt mask during late suspend. Impact on ARMv7 designs (S5Pv210 and Exynos) ============================================ This duplicates setting mask with existing machine code arch/arm/mach-exynos/suspend.c and arch/arm/mach-s5pv210/pm.c but it is not a problem - the wakeup mask register will be written twice. The machine code will be cleaned up later. The difference between implementation here and ARMv7 machine code (arch/arm/mach-*) is the time of writing the mask: 1. The machine code is writing the mask quite late during system suspend path, after offlining secondary CPUs and just before doing actual suspend. 2. The implementation in pinctrl driver uses late suspend ops, therefore it will write the mask much earlier. Hopefully late enough, after all drivers will enable or disable their interrupt wakeups (enable_irq_wake() etc). Impact on ARMv8 designs (Exynos5433 and Exynos7) ================================================ The Suspend to RAM was not supported and external wakeup interrupt mask was not written to HW. This change brings us one step closer to supporting Suspend to RAM. Signed-off-by: Krzysztof Kozlowski Cc: Tomasz Figa Cc: Sylwester Nawrocki Acked-by: Tomasz Figa Tested-by: Marek Szyprowski

ARM: exynos: Define EINT_WAKEUP_MASK registers for S5Pv210 and Exynos5433

2018-07-24T19:50:39Z

S5Pv210 and Exynos5433/Exynos7 have different address of EINT_WAKEUP_MASK register. Rename existing S5P_EINT_WAKEUP_MASK to avoid confusion and add new ones. Signed-off-by: Krzysztof Kozlowski Cc: Tomasz Figa Cc: Sylwester Nawrocki Acked-by: Tomasz Figa Tested-by: Marek Szyprowski