user/sven/linux.git/include/linux/soc, branch v5.18.19

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

2022-03-30T17:11:04Z

Pull clk updates from Stephen Boyd: "There's one large change in the core clk framework here. We change how clk_set_rate_range() works so that the frequency is re-evaulated each time the rate is changed. Previously we wouldn't let clk providers see a rate that was different if it was still within the range, which could be bad for power if the clk could run slower when a range expands. Now the clk provider can decide to do something differently when the constraints change. This broke Nvidia's clk driver so we had to wait for the fix for that to bake a little more in -next. The rate range patch series also introduced a kunit suite for the clk framework that we're going to extend in the next release. It already made it easy to find corner cases in the rate range patches so I'm excited to see it cover more clk code and increase our confidence in core framework patches in the future. I also added a kunit test for the basic clk gate code and that work will continue to cover more basic clk types: muxes, dividers, etc. Beyond the core code we have the usual set of clk driver updates and additions. Qualcomm again dominates the diffstat here with lots more SoCs being supported and i.MX follows afer that with a similar number of SoCs gaining clk drivers. Beyond those large additions there's drivers being modernized to use clk_parent_data so we can move away from global string names for all the clks in an SoC. Finally there's lots of little fixes all over the clk drivers for typos, warnings, and missing clks that aren't critical and get batched up waiting for the next merge window to open. Nothing super big stands out in the driver pile. Full details are below. Core: - Make clk_set_rate_range() re-evaluate the limits each time - Introduce various clk_set_rate_range() tests - Add clk_drop_range() to drop a previously set range New Drivers: - i.MXRT1050 clock driver and bindings - i.MX8DXL clock driver and bindings - i.MX93 clock driver and bindings - NCO blocks on Apple SoCs - Audio clks on StarFive JH7100 RISC-V SoC - Add support for the new Renesas RZ/V2L SoC - Qualcomm SDX65 A7 PLL - Qualcomm SM6350 GPU clks - Qualcomm SM6125, SM6350, QCS2290 display clks - Qualcomm MSM8226 multimedia clks Updates: - Kunit tests for clk-gate implementation - Terminate arrays with sentinels and make that clearer - Cleanup SPDX tags - Fix typos in comments - Mark mux table as const in clk-mux - Make the all_lists array const - Convert Cirrus Logic CS2000P driver to regmap, yamlify DT binding and add support for dynamic mode - Clock configuration on Microchip PolarFire SoCs - Free allocations on probe error in Mediatek clk driver - Modernize Mediatek clk driver by consolidating code - Add watchdog (WDT), I2C, and pin function controller (PFC) clocks on Renesas R-Car S4-8 - Improve the clocks for the Rockchip rk3568 display outputs (parenting, pll-rates) - Use of_device_get_match_data() instead of open-coding on Rockchip rk3568 - Reintroduce the expected fractional-divider behaviour that disappeared with the addition of CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - Remove SYS PLL 1/2 clock gates for i.MX8M* - Remove AUDIO MCLK ROOT from i.MX7D - Add fracn gppll clock type used by i.MX93 - Add new composite clock for i.MX93 - Add missing media mipi phy ref clock for i.MX8MP - Fix off by one in imx_lpcg_parse_clks_from_dt() - Rework for the imx pll14xx - sama7g5: One low priority fix for GCLK of PDMC - Add DMA engine (SYS-DMAC) clocks on Renesas R-Car S4-8 - Add MOST (MediaLB I/F) clocks on Renesas R-Car E3 and D3 - Add CAN-FD clocks on Renesas R-Car V3U - Qualcomm SC8280XP RPMCC - Add some missing clks on Qualcomm MSM8992/MSM8994/MSM8998 SoCs - Rework Qualcomm GCC bindings and convert SDM845 camera bindig to YAML - Convert various Qualcomm drivers to use clk_parent_data - Remove test clocks from various Qualcomm drivers - Crypto engine clks on Qualcomm IPQ806x + more freqs for SDCC/NSS - Qualcomm SM8150 EMAC, PCIe, UFS GDSCs - Better pixel clk frequency support on Qualcomm RCG2 clks" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (227 commits) clk: zynq: Update the parameters to zynq_clk_register_periph_clk clk: zynq: trivial warning fix clk: Drop the rate range on clk_put() clk: test: Test clk_set_rate_range on orphan mux clk: Initialize orphan req_rate dt-bindings: clock: drop useless consumer example dt-bindings: clock: renesas: Make example 'clocks' parsable clk: qcom: gcc-msm8994: Fix gpll4 width dt-bindings: clock: fix dt_binding_check error for qcom,gcc-other.yaml clk: rs9: Add Renesas 9-series PCIe clock generator driver clk: fixed-factor: Introduce devm_clk_hw_register_fixed_factor_index() clk: visconti: prevent array overflow in visconti_clk_register_gates() dt-bindings: clk: rs9: Add Renesas 9-series I2C PCIe clock generator clk: sifive: Move all stuff into SoCs header files from C files clk: sifive: Add SoCs prefix in each SoCs-dependent data riscv: dts: Change the macro name of prci in each device node dt-bindings: change the macro name of prci in header files and example clk: sifive: duplicate the macro definitions for the time being clk: qcom: sm6125-gcc: fix typos in comments clk: ti: clkctrl: fix typos in comments ...

Merge tag 'mailbox-v5.18' of git://git.linaro.org/landing-teams/working/fujitsu/integration

2022-03-27T21:21:57Z

Pull mailbox updates from Jassi Brar: "qcom: - add support for MSM8976 mtk: - enable mt8186 - add ADSP controller driver ti: - use poll mode during suspend tegra: - fix tx channel flush imx: - add i.MX8 SECO MU support - prepare for, and add iMX93 support" * tag 'mailbox-v5.18' of git://git.linaro.org/landing-teams/working/fujitsu/integration: dt-bindings: mailbox: add definition for mt8186 mailbox: ti-msgmgr: Operate mailbox in polled mode during system suspend mailbox: ti-msgmgr: Refactor message read during interrupt handler mailbox: imx: support i.MX93 S401 MU mailbox: imx: support dual interrupts mailbox: imx: extend irq to an array dt-bindings: mailbox: imx-mu: add i.MX93 S4 MU support dt-bindings: mailbox: imx-mu: add i.MX93 MU mailbox: imx: add i.MX8 SECO MU support mailbox: imx: introduce rxdb callback dt-bindings: mailbox: imx-mu: add i.MX8 SECO MU support mailbox: imx: enlarge timeout while reading/writing messages to SCFW mailbox: imx: fix crash in resume on i.mx8ulp mailbox: imx: fix wakeup failure from freeze mode mailbox: mediatek: add support for adsp mailbox controller dt-bindings: mailbox: mtk,adsp-mbox: add mtk adsp-mbox document mailbox: qcom-apcs-ipc: Add compatible for MSM8976 SoC dt-bindings: mailbox: Add compatible for the MSM8976 mailbox: tegra-hsp: Flush whole channel

Merge tag 'arm-drivers-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

2022-03-24T01:23:13Z

Pull ARM driver updates from Arnd Bergmann: "There are a few separately maintained driver subsystems that we merge through the SoC tree, notable changes are: - Memory controller updates, mainly for Tegra and Mediatek SoCs, and clarifications for the memory controller DT bindings - SCMI firmware interface updates, in particular a new transport based on OPTEE and support for atomic operations. - Cleanups to the TEE subsystem, refactoring its memory management For SoC specific drivers without a separate subsystem, changes include - Smaller updates and fixes for TI, AT91/SAMA5, Qualcomm and NXP Layerscape SoCs. - Driver support for Microchip SAMA5D29, Tesla FSD, Renesas RZ/G2L, and Qualcomm SM8450. - Better power management on Mediatek MT81xx, NXP i.MX8MQ and older NVIDIA Tegra chips" * tag 'arm-drivers-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (154 commits) ARM: spear: fix typos in comments soc/microchip: fix invalid free in mpfs_sys_controller_delete soc: s4: Add support for power domains controller dt-bindings: power: add Amlogic s4 power domains bindings ARM: at91: add support in soc driver for new SAMA5D29 soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data dt-bindings: memory: renesas,rpc-if: Document RZ/V2L SoC memory: emif: check the pointer temp in get_device_details() memory: emif: Add check for setup_interrupts dt-bindings: arm: mediatek: mmsys: add support for MT8186 dt-bindings: mediatek: add compatible for MT8186 pwrap soc: mediatek: pwrap: add pwrap driver for MT8186 SoC soc: mediatek: mmsys: add mmsys reset control for MT8186 soc: mediatek: mtk-infracfg: Disable ACP on MT8192 soc: ti: k3-socinfo: Add AM62x JTAG ID soc: mediatek: add MTK mutex support for MT8186 soc: mediatek: mmsys: add mt8186 mmsys routing table soc: mediatek: pm-domains: Add support for mt8186 dt-bindings: power: Add MT8186 power domains soc: mediatek: pm-domains: Add support for mt8195 ...

mailbox: ti-msgmgr: Operate mailbox in polled mode during system suspend

2022-03-13T01:33:30Z

During the system suspend path we must set all queues to operate in polled mode as it is possible for any protocol built using this mailbox, such as TISCI, to require communication during the no irq phase of suspend, and we cannot rely on interrupts there. Polled mode is implemented by allowing the mailbox user to define an RX channel as part of the message that is sent which is what gets polled for a response. If polled mode is enabled, this will immediately be polled for a response at the end of the mailbox send_data op before returning success for the data send or timing out if no response is received. Finally, to ensure polled mode is always enabled during system suspend, iterate through all queues to set RX queues to polled mode during system suspend and disable polled mode for all in the resume handler. Signed-off-by: Dave Gerlach Signed-off-by: Jassi Brar

clk: qcom: smd: Add missing RPM clocks for msm8992/4

2022-03-09T14:53:14Z

XO and MSS_CFG were omitted when first adding the clocks for these SoCs. Add them, and while at it, move the XO clock to the top of the definition list, as ideally everyone should start using it sooner or later.. Fixes: b4297844995f ("clk: qcom: smd: Add support for MSM8992/4 rpm clocks") Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220226214126.21209-2-konrad.dybcio@somainline.org

Merge tag 'qcom-drivers-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers

2022-03-01T18:24:21Z

Qualcomm driver updates for v5.18 This refactors the Qualcomm mdt file loader, to partially decouple it from the SCM peripheral-authentication-service. This is needed as newer platforms, such as the Qualcomm SM8450, require the metadata to remain accessible to TrustZone during a longer time. This is followed by the introduction of remoteproc drivers for SM8450 (Snapdragon 8 Gen 1). It changes the way hardware version differences are handled in the LLCC driver and introduces support for Qualcomm SM8450. While updating the dt binding for LLCC it also introduces the missing SM8350 compatible. The ocmem and aoss drivers gains missing put_device() calls and rpmpd gains a missing check for kcalloc() failure. The SPM driver is updated to avoid instantiating the SPM cpuidle devices if the CPUs aren't controlled by SPM, such as when Snapdragon 8916 operates in 32-bit mode without PSCI. The RPM power-domain driver gains MSM8226 support. Lastly the socinfo driver gains knowledge about a few new SoCs and PMICs. * tag 'qcom-drivers-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (37 commits) soc: qcom: rpmpd: Add MSM8226 support dt-bindings: power: rpmpd: Add MSM8226 to rpmpd binding soc: qcom: mdt_loader: Fix split-firmware condition dt-bindings: arm: msm: Add LLCC compatible for SM8450 dt-bindings: arm: msm: Add LLCC compatible for SM8350 soc: qcom: llcc: Add configuration data for SM8450 SoC soc: qcom: llcc: Update register offsets for newer LLCC HW soc: qcom: llcc: Add missing llcc configuration data soc: qcom: llcc: Add write-cache cacheable support soc: qcom: llcc: Update the logic for version info extraction soc: qcom: llcc: Add support for 16 ways of allocation soc: qcom: socinfo: Add some more PMICs and SoCs firmware: qcom: scm: Add support for MC boot address API firmware: qcom: scm: Drop cpumask parameter from set_boot_addr() firmware: qcom: scm: Simplify set_cold/warm_boot_addr() cpuidle: qcom-spm: Check if any CPU is managed by SPM remoteproc: qcom: pas: Add SM8450 remoteproc support dt-bindings: remoteproc: qcom: pas: Add SM8450 PAS compatibles remoteproc: qcom: pas: Carry PAS metadata context soc: qcom: mdt_loader: Extract PAS operations ... Link: https://lore.kernel.org/r/20220301042055.1804859-1-bjorn.andersson@linaro.org Signed-off-by: Arnd Bergmann

Merge tag 'v5.17-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/drivers

2022-03-01T10:09:42Z

- add power domains support for mt8195 - disable ACP on mt8192 mt8186: - add support for power domains - add mmsys and mutex support needed for DRM - add reset control based on mmsys subsystem - add pmic wrapper * tag 'v5.17-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: dt-bindings: arm: mediatek: mmsys: add support for MT8186 dt-bindings: mediatek: add compatible for MT8186 pwrap soc: mediatek: pwrap: add pwrap driver for MT8186 SoC soc: mediatek: mmsys: add mmsys reset control for MT8186 soc: mediatek: mtk-infracfg: Disable ACP on MT8192 soc: mediatek: add MTK mutex support for MT8186 soc: mediatek: mmsys: add mt8186 mmsys routing table soc: mediatek: pm-domains: Add support for mt8186 dt-bindings: power: Add MT8186 power domains soc: mediatek: pm-domains: Add support for mt8195 soc: mediatek: pm-domains: Move power status offset to power domain data soc: mediatek: pm-domains: Remove unused macro soc: mediatek: pm-domains: Add wakeup capacity support in power domain dt-bindings: power: Add MT8195 power domains Link: https://lore.kernel.org/r/16a53482-5a8c-e95e-8cd4-b8304f110987@gmail.com Signed-off-by: Arnd Bergmann

soc: mediatek: mtk-infracfg: Disable ACP on MT8192

2022-03-01T07:21:28Z

MT8192 contains an experimental Accelerator Coherency Port implementation, which does not work correctly but was unintentionally enabled by default. For correct operation of the GPU, we must set a chicken bit disabling ACP on MT8192. Adapted from the following downstream change to the out-of-tree, legacy Mali GPU driver: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2781271/5 Note this change is required for both Panfrost and the legacy kernel driver. Co-developed-by: Robin Murphy Signed-off-by: Robin Murphy Signed-off-by: Alyssa Rosenzweig Cc: Nick Fan Cc: Nicolas Boichat Cc: Chen-Yu Tsai Cc: Stephen Boyd Cc: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220215184651.12168-1-alyssa.rosenzweig@collabora.com Signed-off-by: Matthias Brugger

soc: mediatek: pm-domains: Add support for mt8186

2022-02-28T11:02:11Z

Add power domain control data in mt8186. Signed-off-by: Chun-Jie Chen Link: https://lore.kernel.org/r/20220215104917.5726-3-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger

soc: mediatek: pm-domains: Add support for mt8195

2022-02-28T11:02:04Z

Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen Reviewed-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger