user/sven/linux.git/include/linux/spi, branch v5.10.178

spi: Switch to signed types for *_native_cs SPI controller fields

2021-09-08T06:49:01Z

commit 35f3f8504c3b60a1ae5576e178b27fc0ddd6157d upstream. While fixing undefined behaviour the commit f60d7270c8a3 ("spi: Avoid undefined behaviour when counting unused native CSs") missed the case when all CSs are GPIOs and thus unused_native_cs will be evaluated to -1 in unsigned representation. This will falsely trigger a condition in the spi_get_gpio_descs(). Switch to signed types for *_native_cs SPI controller fields to fix above. Fixes: f60d7270c8a3 ("spi: Avoid undefined behaviour when counting unused native CSs") Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20210510131242.49455-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown Signed-off-by: Nobuhiro Iwamatsu (CIP) Signed-off-by: Greg Kroah-Hartman

spi: Fix use-after-free with devm_spi_alloc_*

2021-05-14T07:50:16Z

[ Upstream commit 794aaf01444d4e765e2b067cba01cc69c1c68ed9 ] We can't rely on the contents of the devres list during spi_unregister_controller(), as the list is already torn down at the time we perform devres_find() for devm_spi_release_controller. This causes devices registered with devm_spi_alloc_{master,slave}() to be mistakenly identified as legacy, non-devm managed devices and have their reference counters decremented below 0. ------------[ cut here ]------------ WARNING: CPU: 1 PID: 660 at lib/refcount.c:28 refcount_warn_saturate+0x108/0x174 [] (refcount_warn_saturate) from [] (kobject_put+0x90/0x98) [] (kobject_put) from [] (put_device+0x20/0x24) r4:b6700140 [] (put_device) from [] (devm_spi_release_controller+0x3c/0x40) [] (devm_spi_release_controller) from [] (release_nodes+0x84/0xc4) r5:b6700180 r4:b6700100 [] (release_nodes) from [] (devres_release_all+0x5c/0x60) r8:b1638c54 r7:b117ad94 r6:b1638c10 r5:b117ad94 r4:b163dc10 [] (devres_release_all) from [] (__device_release_driver+0x144/0x1ec) r5:b117ad94 r4:b163dc10 [] (__device_release_driver) from [] (device_driver_detach+0x84/0xa0) r9:00000000 r8:00000000 r7:b117ad94 r6:b163dc54 r5:b1638c10 r4:b163dc10 [] (device_driver_detach) from [] (unbind_store+0xe4/0xf8) Instead, determine the devm allocation state as a flag on the controller which is guaranteed to be stable during cleanup. Fixes: 5e844cc37a5c ("spi: Introduce device-managed SPI controller allocation") Signed-off-by: William A. Kennington III Link: https://lore.kernel.org/r/20210407095527.2771582-1-wak@google.com Signed-off-by: Mark Brown Signed-off-by: Sasha Levin

spi: Introduce device-managed SPI controller allocation

2020-11-12T15:05:34Z

SPI driver probing currently comprises two steps, whereas removal comprises only one step: spi_alloc_master() spi_register_controller() spi_unregister_controller() That's because spi_unregister_controller() calls device_unregister() instead of device_del(), thereby releasing the reference on the spi_controller which was obtained by spi_alloc_master(). An SPI driver's private data is contained in the same memory allocation as the spi_controller struct. Thus, once spi_unregister_controller() has been called, the private data is inaccessible. But some drivers need to access it after spi_unregister_controller() to perform further teardown steps. Introduce devm_spi_alloc_master() and devm_spi_alloc_slave(), which release a reference on the spi_controller struct only after the driver has unbound, thereby keeping the memory allocation accessible. Change spi_unregister_controller() to not release a reference if the spi_controller was allocated by one of these new devm functions. The present commit is small enough to be backportable to stable. It allows fixing drivers which use the private data in their ->remove() hook after it's been freed. It also allows fixing drivers which neglect to release a reference on the spi_controller in the probe error path. Long-term, most SPI drivers shall be moved over to the devm functions introduced herein. The few that can't shall be changed in a treewide commit to explicitly release the last reference on the controller. That commit shall amend spi_unregister_controller() to no longer release a reference, thereby completing the migration. As a result, the behaviour will be less surprising and more consistent with subsystems such as IIO, which also includes the private data in the allocation of the generic iio_dev struct, but calls device_del() in iio_device_unregister(). Signed-off-by: Lukas Wunner Link: https://lore.kernel.org/r/272bae2ef08abd21388c98e23729886663d19192.1605121038.git.lukas@wunner.de Signed-off-by: Mark Brown

Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

2020-10-24T17:33:08Z

Pull ARM SoC platform updates from Olof Johansson: "SoC changes, a substantial part of this is cleanup of some of the older platforms that used to have a bunch of board files. In particular: - Remove non-DT i.MX platforms that haven't seen activity in years, it's time to remove them. - A bunch of cleanup and removal of platform data for TI/OMAP platforms, moving over to genpd for power/reset control (yay!) - Major cleanup of Samsung S3C24xx and S3C64xx platforms, moving them closer to multiplatform support (not quite there yet, but getting close). There are a few other changes too, smaller fixlets, etc. For new platform support, the primary ones are: - New SoC: Hisilicon SD5203, ARM926EJ-S platform. - Cpufreq support for i.MX7ULP" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (121 commits) ARM: mstar: Select MStar intc ARM: stm32: Replace HTTP links with HTTPS ones ARM: debug: add UART early console support for SD5203 ARM: hisi: add support for SD5203 SoC ARM: omap3: enable off mode automatically clk: imx: imx35: Remove mx35_clocks_init() clk: imx: imx31: Remove mx31_clocks_init() clk: imx: imx27: Remove mx27_clocks_init() ARM: imx: Remove unused definitions ARM: imx35: Retrieve the IIM base address from devicetree ARM: imx3: Retrieve the AVIC base address from devicetree ARM: imx3: Retrieve the CCM base address from devicetree ARM: imx31: Retrieve the IIM base address from devicetree ARM: imx27: Retrieve the CCM base address from devicetree ARM: imx27: Retrieve the SYSCTRL base address from devicetree ARM: s3c64xx: bring back notes from removed debug-macro.S ARM: s3c24xx: fix Wunused-variable warning on !MMU ARM: samsung: fix PM debug build with DEBUG_LL but !MMU MAINTAINERS: mark linux-samsung-soc list non-moderated ARM: imx: Remove remnant board file support pieces ...

eeprom: at25: allow page sizes greater than 16 bit

2020-08-28T10:08:08Z

Storage technologies like FRAM have no "write pages", the whole chip can be written within one SPI transfer. For these chips, the page size can be set equal to the device size. Currently available devices are already bigger than 64 kiB. Signed-off-by: Christian Eggers Link: https://lore.kernel.org/r/20200727111218.26926-1-ceggers@arri.de Signed-off-by: Greg Kroah-Hartman

ARM: s3c24xx: spi: avoid hardcoding fiq number in driver

2020-08-20T15:43:45Z

The IRQ_EINT0 constant is a platform detail that is defined in mach/irqs.h and not visible to drivers once that header is made private. Since the same calculation already happens in s3c24xx_set_fiq, just return the value from there. Signed-off-by: Arnd Bergmann Acked-by: Mark Brown Link: https://lore.kernel.org/r/20200806182059.2431-31-krzk@kernel.org Signed-off-by: Krzysztof Kozlowski

ARM: s3c24xx: move spi fiq handler into platform

2020-08-19T19:45:38Z

The fiq handler needs access to some register definitions that should not be used directly by device drivers. Since this is closely related to the irqchip driver anyway, move it into the same place. Signed-off-by: Arnd Bergmann [krzk: Add a header guard in include/linux/spi/s3c24xx-fiq.h, fix SPDX comment style, update maintainer's entry] Co-developed-by: Krzysztof Kozlowski Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200806182059.2431-23-krzk%40kernel.org Acked-by: Mark Brown

spi: correct kernel-doc inconsistency

2020-07-27T13:55:22Z

Silence documentation build warnings by correcting kernel-doc comment for spi_transfer struct. Signed-off-by: Colton Lewis Link: https://lore.kernel.org/r/20200725050242.279548-1-colton.w.lewis@protonmail.com Signed-off-by: Mark Brown

spi: fix duplicated word in

2020-07-16T23:55:22Z

Change doubled word "as" to "as a". Change "Return: Return:" in kernel-doc notation to have only one "Return:". Signed-off-by: Randy Dunlap Cc: Mark Brown Cc: linux-spi@vger.kernel.org Link: https://lore.kernel.org/r/40354d64-be71-3952-a980-63a76a278145@infradead.org Signed-off-by: Mark Brown

Merge series "mtd: spi-nor: add xSPI Octal DTR support" from Pratyush Yadav :

2020-07-14T16:38:47Z

Hi, This series adds support for octal DTR flashes in the spi-nor framework, and then adds hooks for the Cypress Semper and Mircom Xcella flashes to allow running them in octal DTR mode. This series assumes that the flash is handed to the kernel in Legacy SPI mode. Tested on TI J721e EVM with 1-bit ECC on the Cypress flash. Changes in v10: - Rebase on latest linux-next/master. Drop a couple patches that made it in the previous release. - Move the code that sets 20 dummy cycles for MT35XU512ABA to its octal enable function. This way, if the controller doesn't support 8D mode 20 dummy cycles won't be used. Changes in v9: - Do not use '& 0xff' to get the opcode LSB in spi-mxic and spi-zynq-qspi. The cast to u8 will do that anyway. - Do not use if (opcode) as a check for whether the command phase exists in spi-zynq-qspi because the opcode 0 can be valid. Use the new cmd.nbytes instead. Changes in v8: - Move controller changes in spi-mxic to the commit which introduces 2-byte opcodes to avoid problems when bisecting. - Replace usage of sizeof(op->cmd.opcode) with op->cmd.nbytes. - Extract opcode in spi-zynq-qspi instead of using &op->cmd.opcode. Changes in v7: - Reject ops with more than 1 command byte in spi_mem_default_supports_op(). - Reject ops with more than 1 command byte in atmel and mtk controllers. - Reject ops with 0 command bytes in spi_mem_check_op(). - Set cmd.nbytes to 1 when using SPI_MEM_OP_CMD(). - Avoid endianness problems in spi-mxic. Changes in v6: - Instead of hard-coding 8D-8D-8D Fast Read dummy cycles to 20, find them out from the Profile 1.0 table. Changes in v5: - Do not enable stateful X-X-X modes if the reset line is broken. - Instead of setting SNOR_READ_HWCAPS_8_8_8_DTR from Profile 1.0 table parsing, do it in spi_nor_info_init_params() instead based on the SPI_NOR_OCTAL_DTR_READ flag instead. - Set SNOR_HWCAPS_PP_8_8_8_DTR in s28hs post_sfdp hook since this capability is no longer set in Profile 1.0 parsing. - Instead of just checking for spi_nor_get_protocol_width() in spi_nor_octal_dtr_enable(), make sure the protocol is SNOR_PROTO_8_8_8_DTR since get_protocol_width() only cares about data width. - Drop flag SPI_NOR_SOFT_RESET. Instead, discover soft reset capability via BFPT. - Do not make an invalid Quad Enable BFPT field a fatal error. Silently ignore it by assuming no quad enable bit is present. - Set dummy cycles for Cypress Semper flash to 24 instead of 20. This allows for 200MHz operation in 8D mode compared to the 166MHz with 20. - Rename spi_nor_cypress_octal_enable() to spi_nor_cypress_octal_dtr_enable(). - Update spi-mtk-nor.c to reject DTR ops since it doesn't call spi_mem_default_supports_op(). Changes in v4: - Refactor the series to use the new spi-nor framework with the manufacturer-specific bits separated from the core. - Add support for Micron MT35XU512ABA. - Use cmd.nbytes as the criteria of whether the data phase exists or not instead of cmd.buf.in || cmd.buf.out in spi_nor_spimem_setup_op(). - Update Read FSR to use the same dummy cycles and address width as Read SR. - Fix BFPT parsing stopping too early for JESD216 rev B flashes. - Use 2 byte reads for Read SR and FSR commands in DTR mode. Changes in v3: - Drop the DT properties "spi-rx-dtr" and "spi-tx-dtr". Instead, if later a need is felt to disable DTR in case someone has a board with Octal DTR capable flash but does not support DTR transactions for some reason, a property like "spi-no-dtr" can be added. - Remove mode bits SPI_RX_DTR and SPI_TX_DTR. - Remove the Cadence Quadspi controller patch to un-block this series. I will submit it as a separate patch. - Rebase on latest 'master' and fix merge conflicts. - Update read and write dirmap templates to use DTR. - Rename 'is_dtr' to 'dtr'. - Make 'dtr' a bitfield. - Reject DTR ops in spi_mem_default_supports_op(). - Update atmel-quadspi to reject DTR ops. All other controller drivers call spi_mem_default_supports_op() so they will automatically reject DTR ops. - Add support for both enabling and disabling DTR modes. - Perform a Software Reset on flashes that support it when shutting down. - Disable Octal DTR mode on suspend, and re-enable it on resume. - Drop enum 'spi_mem_cmd_ext' and make command opcode u16 instead. Update spi-nor to use the 2-byte command instead of the command extension. Since we still need a "extension type", mode that enum to spi-nor and name it 'spi_nor_cmd_ext'. - Default variable address width to 3 to fix SMPT parsing. - Drop non-volatile change to uniform sector mode and rely on parsing SMPT. Changes in v2: - Add DT properties "spi-rx-dtr" and "spi-tx-dtr" to allow expressing DTR capabilities. - Set the mode bits SPI_RX_DTR and SPI_TX_DTR when we discover the DT properties "spi-rx-dtr" and spi-tx-dtr". - spi_nor_cypress_octal_enable() was updating nor->params.read[] with the intention of setting the correct number of dummy cycles. But this function is called _after_ selecting the read so setting nor->params.read[] will have no effect. So, update nor->read_dummy directly. - Fix spi_nor_spimem_check_readop() and spi_nor_spimem_check_pp() passing nor->read_proto and nor->write_proto to spi_nor_spimem_setup_op() instead of read->proto and pp->proto respectively. - Move the call to cqspi_setup_opcode_ext() inside cqspi_enable_dtr(). This avoids repeating the 'if (f_pdata->is_dtr) cqspi_setup_opcode_ext()...` snippet multiple times. - Call the default 'supports_op()' from cqspi_supports_mem_op(). This makes sure the buswidth requirements are also enforced along with the DTR requirements. - Drop the 'is_dtr' argument from spi_check_dtr_req(). We only call it when a phase is DTR so it is redundant. Pratyush Yadav (17): spi: spi-mem: allow specifying whether an op is DTR or not spi: spi-mem: allow specifying a command's extension spi: atmel-quadspi: reject DTR ops spi: spi-mtk-nor: reject DTR ops mtd: spi-nor: add support for DTR protocol mtd: spi-nor: sfdp: get command opcode extension type from BFPT mtd: spi-nor: sfdp: parse xSPI Profile 1.0 table mtd: spi-nor: core: use dummy cycle and address width info from SFDP mtd: spi-nor: core: do 2 byte reads for SR and FSR in DTR mode mtd: spi-nor: core: enable octal DTR mode when possible mtd: spi-nor: sfdp: do not make invalid quad enable fatal mtd: spi-nor: sfdp: detect Soft Reset sequence support from BFPT mtd: spi-nor: core: perform a Soft Reset on shutdown mtd: spi-nor: core: disable Octal DTR mode on suspend. mtd: spi-nor: core: expose spi_nor_default_setup() in core.h mtd: spi-nor: spansion: add support for Cypress Semper flash mtd: spi-nor: micron-st: allow using MT35XU512ABA in Octal DTR mode drivers/mtd/spi-nor/core.c | 446 +++++++++++++++++++++++++++----- drivers/mtd/spi-nor/core.h | 22 ++ drivers/mtd/spi-nor/micron-st.c | 103 +++++++- drivers/mtd/spi-nor/sfdp.c | 131 +++++++++- drivers/mtd/spi-nor/sfdp.h | 8 + drivers/mtd/spi-nor/spansion.c | 166 ++++++++++++ drivers/spi/atmel-quadspi.c | 6 + drivers/spi/spi-mem.c | 16 +- drivers/spi/spi-mtk-nor.c | 10 +- drivers/spi/spi-mxic.c | 3 +- drivers/spi/spi-zynq-qspi.c | 11 +- include/linux/mtd/spi-nor.h | 53 +++- include/linux/spi/spi-mem.h | 14 +- 13 files changed, 889 insertions(+), 100 deletions(-) -- 2.27.0 base-commit: b3a9e3b9622ae10064826dccb4f7a52bd88c7407 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel