user/sven/linux.git/include/linux/stmmac.h, branch v3.10.44

Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial

2012-12-13T20:00:02Z

Pull trivial branch from Jiri Kosina: "Usual stuff -- comment/printk typo fixes, documentation updates, dead code elimination." * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (39 commits) HOWTO: fix double words typo x86 mtrr: fix comment typo in mtrr_bp_init propagate name change to comments in kernel source doc: Update the name of profiling based on sysfs treewide: Fix typos in various drivers treewide: Fix typos in various Kconfig wireless: mwifiex: Fix typo in wireless/mwifiex driver messages: i2o: Fix typo in messages/i2o scripts/kernel-doc: check that non-void fcts describe their return value Kernel-doc: Convention: Use a "Return" section to describe return values radeon: Fix typo and copy/paste error in comments doc: Remove unnecessary declarations from Documentation/accounting/getdelays.c various: Fix spelling of "asynchronous" in comments. Fix misspellings of "whether" in comments. eisa: Fix spelling of "asynchronous". various: Fix spelling of "registered" in comments. doc: fix quite a few typos within Documentation target: iscsi: fix comment typos in target/iscsi drivers treewide: fix typo of "suport" in various comments and Kconfig treewide: fix typo of "suppport" in various comments ...

stmmac: add Rx watchdog support to mitigate the DMA irqs

2012-11-26T22:22:12Z

GMAC devices newer than databook 3.40 has an embedded timer that can be used for mitigating the number of interrupts. So this patch adds this optimizations. At any rate, the Rx watchdog can be disable (on bugged HW) by passing from the platform the riwt_off field. In this implementation the rx timer stored in the Reg9 is fixed to the max value. This will be tuned by using ethtool. V2: added a platform parameter to force to disable the rx-watchdog for example on new core where it is bugged. V3: do not disable NAPI when Rx watchdog is used. V4: a new extra statistic field has been added to show the early receive status in the interrupt handler. This patch also adds an extra check to avoid to call napi_schedule when the DMA_INTR_ENA_RIE bit is disabled in the Interrupt Mask register. Signed-off-by: Giuseppe Cavallaro Signed-off-by: David S. Miller

treewide: fix typo of "suport" in various comments and Kconfig

2012-11-19T13:16:09Z

Signed-off-by: Masanari Iida Signed-off-by: Jiri Kosina

net:stmmac: Remove bus_id from mdio platform data.

2012-08-31T20:11:28Z

This patch removes bus_id from mdio platform data, The reason to remove bus_id is, stmmac mdio bus_id is always same as stmmac bus-id, so there is no point in passing this in different variable. Also stmmac ethernet driver connects to phy with bus_id passed its platform data. So, having single bus-id is much simpler. Signed-off-by: Srinivas Kandagatla Signed-off-by: David S. Miller

stmmac: add mixed burst for DMA

2012-05-14T22:53:19Z

In mixed burst (MB) mode, the AHB master always initiates the bursts with fixed-size when the DMA requests transfers of size less than or equal to 16 beats. This patch adds the MB support and the flag that can be passed from the platform to select it. MB mode can also give some benefits in terms of performances on some platforms. v2: fixed Coding Style Signed-off-by: Giuseppe Cavallaro Signed-off-by: David S. Miller

stmmac: use custom init/exit functions in pm ops

2012-04-20T00:08:44Z

Freeze and restore can call the custom init/exit functions. Also the patch adds a custom data field that can be used for storing platform data useful on restore the embedded setup (e.g. GPIO, SYSCFG). Signed-off-by: Francesco Virlinzi Signed-off-by: Giuseppe Cavallaro Signed-off-by: David S. Miller

stmmac: extend CSR Clock Range programming

2012-04-04T22:39:24Z

The CSR Clock Range has been reworked and new macros has been added in the platform header to allow the CSR Clock Range selection in the GMII Address Register. The previous work didn't add the other fields that can be used to achieve MDC clock of frequency higher than the IEEE 802.3 specified frequency limit of 2.5 MHz and program a clock divider of lower value. On such platforms, these are used indeed so this patch adds them. Signed-off-by: Giuseppe Cavallaro Signed-off-by: David S. Miller

stmmac: re-work the internal GMAC DMA platf parameters

2012-04-04T22:39:24Z

This patch re-works the internal GMAC DMA parameters passed from the platform. In the past, we only passed the pbl but, with new core, other parameters can be passed and are mandatory on some platforms. New parameters are documented in stmmac.txt because this patch has an impact for many platforms. Signed-off-by: Shiraz Hashim Signed-off-by: Vikas Manocha Signed-off-by: Deepak Sikri Hacked-by: Giuseppe Cavallaro Signed-off-by: David S. Miller

stmmac: Define MDC clock selection macros

2012-04-04T22:39:23Z

The patch adds the macros to be used for MDC clock selection. The MDC clock frequency is based on scaled system clock, and has to be confined to a range of 1-2.5 MHz. Based on the input CSR clock, the scaling factor has to be selected. The platform specific code will provide the default value of this scaling factor, based on the input CSR clock. There is an option to set MDC clock higher than the IEEE 802.3 specified frequency limit of 2.5 MHz. This applies for the interfacing chips that support higher MDC clocks. The resultant higher clock of 12.5 MHz requires additional Macros to be defined for the clock divider corresponding to the to the following selection. ----------------------------------------- Selection MDC Clock ----------------------------------------- 1000 clk_csr_i/4 1001 clk_csr_i/6 1010 clk_csr_i/8 1011 clk_csr_i/10 1100 clk_csr_i/12 1101 clk_csr_i/14 1110 clk_csr_i/16 1111 clk_csr_i/18 This support has to be added both in the include file, as well as driver. The driver need to program the registers based on the interfacing chips. This would be more board specific information and needs to be passed through the platform code to the driver. This work would be carried out in the future patch set release. Signed-off-by: Deepak Sikri Acked-by: Giuseppe Cavallaro Signed-off-by: David S. Miller

stmmac: Define CSUM offload engine Types

2012-04-04T22:39:23Z

This patch explicitly defines the CSUM offload engine type which need (not mandatory) to be passed from the platform code. STMMAC core supports two check sum offload engine types- Type-1 & Type-2. Also, there are STMMAC cores that do not have the check sum offload capabilities. The behaviour of Type-1 & Type-2 cores related to provision of checksum increases the packet length for Type-1 cores by 2, as the checksum is appended at the end of data packet and the same is made accountable in the DMA status. The STMMAC cores beyond Version-3.5 provide HW interface registers which allows the user to read the HW capabilities, while to support the previous cores the information related to HW capabilities has to be provided from the platform code. The Type-1 cores which do not have the HW register interface need this information. This patch also updates the driver's doc. Signed-off-by: Deepak Sikri Hacked-by: Giuseppe Cavallaro Signed-off-by: David S. Miller