<feed xmlns='http://www.w3.org/2005/Atom'>
<title>user/sven/linux.git/include/linux/stmmac.h, branch v5.9.8</title>
<subtitle>Linux Kernel
</subtitle>
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<updated>2020-04-21T22:54:45Z</updated>
<entry>
<title>net: stmmac: Enable SERDES power up/down sequence</title>
<updated>2020-04-21T22:54:45Z</updated>
<author>
<name>Voon Weifeng</name>
<email>weifeng.voon@intel.com</email>
</author>
<published>2020-04-20T15:42:52Z</published>
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<id>urn:sha1:b9663b7ca6ff780555108394c9c1b409f63b99a7</id>
<content type='text'>
This patch is to enable Intel SERDES power up/down sequence. The SERDES
converts 8/10 bits data to SGMII signal. Below is an example of
HW configuration for SGMII mode. The SERDES is located in the PHY IF
in the diagram below.

&lt;-----------------GBE Controller----------&gt;|&lt;--External PHY chip--&gt;
+----------+         +----+            +---+           +----------+
|   EQoS   | &lt;-GMII-&gt;| DW | &lt; ------ &gt; |PHY| &lt;-SGMII-&gt; | External |
|   MAC    |         |xPCS|            |IF |           | PHY      |
+----------+         +----+            +---+           +----------+
       ^               ^                 ^                ^
       |               |                 |                |
       +---------------------MDIO-------------------------+

PHY IF configuration and status registers are accessible through
mdio address 0x15 which is defined as mdio_adhoc_addr. During D0,
The driver will need to power up PHY IF by changing the power state
to P0. Likewise, for D3, the driver sets PHY IF power state to P3.

Signed-off-by: Voon Weifeng &lt;weifeng.voon@intel.com&gt;
Signed-off-by: Ong Boon Leong &lt;boon.leong.ong@intel.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net: stmmac: Integrate it with DesignWare XPCS</title>
<updated>2020-03-10T03:13:16Z</updated>
<author>
<name>Jose Abreu</name>
<email>Jose.Abreu@synopsys.com</email>
</author>
<published>2020-03-09T08:36:27Z</published>
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<id>urn:sha1:f213bbe8a9d6ba1d0adf424787c02f361ea78c38</id>
<content type='text'>
Adds all the necessary logic so that stmmac can be used with Synopsys
DesignWare XPCS.

Signed-off-by: Jose Abreu &lt;Jose.Abreu@synopsys.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net: stmmac: Initial support for TBS</title>
<updated>2020-01-14T02:31:48Z</updated>
<author>
<name>Jose Abreu</name>
<email>Jose.Abreu@synopsys.com</email>
</author>
<published>2020-01-13T16:24:09Z</published>
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<id>urn:sha1:579a25a854d482bc9d0f9ab0e07ba32fb66bd9e3</id>
<content type='text'>
Adds the initial hooks for TBS support. This needs a 32 byte descriptor
in order for it to work with current HW. Adds all the logic for Enhanced
Descriptors in main core but no HW related logic for now.

Changes from v2:
- Use bitfield for TBS status / support (Jakub)
- Remove unneeded cache alignment (Jakub)
- Fix checkpatch issues

Signed-off-by: Jose Abreu &lt;Jose.Abreu@synopsys.com&gt;
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>net: stmmac: Add basic EST support for GMAC5+</title>
<updated>2019-12-18T20:17:10Z</updated>
<author>
<name>Jose Abreu</name>
<email>joabreu@synopsys.com</email>
</author>
<published>2019-12-18T10:33:05Z</published>
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<id>urn:sha1:504723af0d85434be5fb6f2dde0b62644a7f1ead</id>
<content type='text'>
Adds the support for EST in GMAC5+ cores. This feature allows to offload
scheduling of queues opening time to the IP.

Signed-off-by: Jose Abreu &lt;joabreu@synopsys.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net: of_get_phy_mode: Change API to solve int/unit warnings</title>
<updated>2019-11-04T19:21:25Z</updated>
<author>
<name>Andrew Lunn</name>
<email>andrew@lunn.ch</email>
</author>
<published>2019-11-04T01:40:33Z</published>
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<id>urn:sha1:0c65b2b90d13c1deaee6449304dd367c5d4eb8ae</id>
<content type='text'>
Before this change of_get_phy_mode() returned an enum,
phy_interface_t. On error, -ENODEV etc, is returned. If the result of
the function is stored in a variable of type phy_interface_t, and the
compiler has decided to represent this as an unsigned int, comparision
with -ENODEV etc, is a signed vs unsigned comparision.

Fix this problem by changing the API. Make the function return an
error, or 0 on success, and pass a pointer, of type phy_interface_t,
where the phy mode should be stored.

v2:
Return with *interface set to PHY_INTERFACE_MODE_NA on error.
Add error checks to all users of of_get_phy_mode()
Fixup a few reverse christmas tree errors
Fixup a few slightly malformed reverse christmas trees

v3:
Fix 0-day reported errors.

Reported-by: Dan Carpenter &lt;dan.carpenter@oracle.com&gt;
Signed-off-by: Andrew Lunn &lt;andrew@lunn.ch&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net: stmmac: Only enable enhanced addressing mode when needed</title>
<updated>2019-10-03T19:00:50Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2019-10-02T14:52:57Z</published>
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<id>urn:sha1:968a2978cb39a754750d35a47049781660682a31</id>
<content type='text'>
Enhanced addressing mode is only required when more than 32 bits need to
be addressed. Add a DMA configuration parameter to enable this mode only
when needed.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net: stmmac: implement support for passive mode converters via dt</title>
<updated>2019-09-11T14:27:09Z</updated>
<author>
<name>Alexandru Ardelean</name>
<email>alexandru.ardelean@analog.com</email>
</author>
<published>2019-09-06T13:02:55Z</published>
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<id>urn:sha1:0060c8783330ab60deb96f9d6bb7abfe4664765d</id>
<content type='text'>
In-between the MAC &amp; PHY there can be a mode converter, which converts one
mode to another (e.g. GMII-to-RGMII).

The converter, can be passive (i.e. no driver or OS/SW information
required), so the MAC &amp; PHY need to be configured differently.

For the `stmmac` driver, this is implemented via a `mac-mode` property in
the device-tree, which configures the MAC into a certain mode, and for the
PHY a `phy_interface` field will hold the mode of the PHY. The mode of the
PHY will be passed to the PHY and from there-on it work in a different
mode. If unspecified, the default `phy-mode` will be used for both.

Signed-off-by: Alexandru Ardelean &lt;alexandru.ardelean@analog.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net: stmmac: setup higher frequency clk support for EHL &amp; TGL</title>
<updated>2019-08-28T04:59:38Z</updated>
<author>
<name>Voon Weifeng</name>
<email>weifeng.voon@intel.com</email>
</author>
<published>2019-08-27T01:38:11Z</published>
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<id>urn:sha1:190f73ab4c43ecfc8e93843fe249efeff7d69a90</id>
<content type='text'>
EHL DW EQOS is running on a 200MHz clock. Setting up stmmac-clk,
ptp clock and ptp_max_adj to 200MHz.

Signed-off-by: Voon Weifeng &lt;weifeng.voon@intel.com&gt;
Signed-off-by: Ong Boon Leong &lt;boon.leong.ong@intel.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net: stmmac: Implement RSS and enable it in XGMAC core</title>
<updated>2019-08-09T05:20:19Z</updated>
<author>
<name>Jose Abreu</name>
<email>Jose.Abreu@synopsys.com</email>
</author>
<published>2019-08-07T08:03:12Z</published>
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<id>urn:sha1:76067459c686c4fc6352613e5a6a54e4ffef2861</id>
<content type='text'>
Implement the RSS functionality and add the corresponding callbacks in
XGMAC core.

Changes from v1:
	- Do not use magic constants (Jakub)
	- Use ethtool_rxfh_indir_default() (Jakub)

Signed-off-by: Jose Abreu &lt;joabreu@synopsys.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net: stmmac: Make MDIO bus reset optional</title>
<updated>2019-07-27T20:52:26Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2019-07-26T10:27:40Z</published>
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<id>urn:sha1:1a981c0586c038710227eb740350f291e77ce365</id>
<content type='text'>
The Tegra EQOS driver already resets the MDIO bus at probe time via the
reset GPIO specified in the phy-reset-gpios device tree property. There
is no need to reset the bus again later on.

This avoids the need to query the device tree for the snps,reset GPIO,
which is not part of the Tegra EQOS device tree bindings. This quiesces
an error message from the generic bus reset code if it doesn't find the
snps,reset related delays.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
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