user/sven/linux.git/include/soc/fsl, branch v4.9.243

fsl/qe: add bit description for SYNL register for GUMR

2018-04-13T17:48:01Z

[ Upstream commit c7f235a7c2d09b1b83671ba2d93ebee981554467 ] Add the bitmask for the two bit SYNL register according to the QUICK Engine Reference Manual. Signed-off-by: Holger Brunck Cc: Zhao Qiang Signed-off-by: David S. Miller Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman

net: ethernet: ucc_geth: fix MEM_PART_MURAM mode

2018-03-24T10:00:19Z

[ Upstream commit 8b8642af15ed14b9a7a34d3401afbcc274533e13 ] Since commit 5093bb965a163 ("powerpc/QE: switch to the cpm_muram implementation"), muram area is not part of immrbar mapping anymore so immrbar_virt_to_phys() is not usable anymore. Fixes: 5093bb965a163 ("powerpc/QE: switch to the cpm_muram implementation") Signed-off-by: Christophe Leroy Acked-by: David S. Miller Acked-by: Li Yang Signed-off-by: Scott Wood Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman

soc/fsl: Introduce DPAA 1.x QMan device driver

2016-09-25T07:38:59Z

This driver enables the Freescale DPAA 1.x Queue Manager block. QMan is a hardware accelerator that manages frame queues. It allows CPUs and other accelerators connected to the SoC datapath to enqueue and dequeue ethernet frames, thus providing the infrastructure for data exchange among CPUs and datapath accelerators. Signed-off-by: Roy Pledge Signed-off-by: Claudiu Manoil Signed-off-by: Scott Wood

soc/fsl: Introduce DPAA 1.x BMan device driver

2016-09-25T07:38:58Z

This driver enables the Freescale DPAA 1.x Buffer Manager block. BMan is a hardware accelerator that manages buffer pools. It allows CPUs and other accelerators connected to the SoC datapath to acquire and release buffers during data processing. Signed-off-by: Roy Pledge Signed-off-by: Claudiu Manoil Signed-off-by: Scott Wood

fsl/qe: Do not prefix header guard with CONFIG_

2016-06-08T18:08:01Z

The CONFIG_ prefix should only be used for options which can be configured through Kconfig and not for guarding headers. Signed-off-by: Andreas Ziegler Signed-off-by: David S. Miller

drivers/net: support hdlc function for QE-UCC

2016-06-07T22:56:31Z

The driver add hdlc support for Freescale QUICC Engine. It support NMSI and TSA mode. Signed-off-by: Zhao Qiang Signed-off-by: David S. Miller

fsl/qe: Add QE TDM lib

2016-06-07T22:56:31Z

QE has module to support TDM, some other protocols supported by QE are based on TDM. add a qe-tdm lib, this lib provides functions to the protocols using TDM to configurate QE-TDM. Signed-off-by: Zhao Qiang Signed-off-by: David S. Miller

fsl/qe: Make regs resouce_size_t

2016-06-07T22:56:31Z

Signed-off-by: Zhao Qiang Signed-off-by: David S. Miller

fsl/qe: setup clock source for TDM mode

2016-06-07T22:56:30Z

Add tdm clock configuration in both qe clock system and ucc fast controller. Signed-off-by: Zhao Qiang Signed-off-by: David S. Miller

fsl/qe: add rx_sync and tx_sync for TDM mode

2016-06-07T22:56:30Z

Rx_sync and tx_sync are used by QE-TDM mode, add them to struct ucc_fast_info. Signed-off-by: Zhao Qiang Signed-off-by: David S. Miller