<feed xmlns='http://www.w3.org/2005/Atom'>
<title>user/sven/linux.git/include/uapi/drm/amdgpu_drm.h, branch v5.10.64</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v5.10.64</id>
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<updated>2020-08-06T19:45:52Z</updated>
<entry>
<title>drm/amdgpu: new ids flag for tmz (v2)</title>
<updated>2020-08-06T19:45:52Z</updated>
<author>
<name>Pierre-Eric Pelloux-Prayer</name>
<email>pierre-eric.pelloux-prayer@amd.com</email>
</author>
<published>2020-07-30T13:54:59Z</published>
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<id>urn:sha1:16c642ec3fe9a144fbe1e97dc56f13a6308f1381</id>
<content type='text'>
Allows UMD to know if TMZ is supported and enabled.

This commit also bumps KMS_DRIVER_MINOR because if we don't
UMD can't tell if "ids_flags &amp; AMDGPU_IDS_FLAGS_TMZ == 0" means
"tmz is not enabled" or "tmz may be enabled but the kernel doesn't
report it".

v2: use amdgpu_is_tmz() and reworded commit message.

Signed-off-by: Pierre-Eric Pelloux-Prayer &lt;pierre-eric.pelloux-prayer@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Improve the MTYPE comments</title>
<updated>2020-05-28T18:00:50Z</updated>
<author>
<name>Yong Zhao</name>
<email>Yong.Zhao@amd.com</email>
</author>
<published>2020-05-27T00:53:21Z</published>
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<id>urn:sha1:130c88931f6cbdb4513d307b4a13fcfff08a8041</id>
<content type='text'>
Use words insteads of acronyms for better understanding.

Signed-off-by: Yong Zhao &lt;Yong.Zhao@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add a UAPI flag for user to call mem_sync</title>
<updated>2020-05-18T15:24:21Z</updated>
<author>
<name>Andrey Grodzovsky</name>
<email>andrey.grodzovsky@amd.com</email>
</author>
<published>2020-04-28T05:28:43Z</published>
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<id>urn:sha1:43c8546bcd854806736d8a635a0d696504dd4c21</id>
<content type='text'>
When this flag is set in the CS IB flags, it causes
a memory cache flush of the GFX.

v2:
Move new flag to drm_amdgpu_cs_chunk_ib.flags
Bump up UAPI version
Remove condition on job != null to emit mem_sync

Signed-off-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Reviewed-by: Luben Tuikov &lt;luben.tuikov@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Move to a per-IB secure flag (TMZ)</title>
<updated>2020-04-28T20:20:29Z</updated>
<author>
<name>Luben Tuikov</name>
<email>luben.tuikov@amd.com</email>
</author>
<published>2020-04-22T21:56:56Z</published>
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<id>urn:sha1:0bb5d5b03f78aeb5f87d47877eb15532875c64da</id>
<content type='text'>
Move from a per-CS secure flag (TMZ) to a per-IB
secure flag.

Signed-off-by: Luben Tuikov &lt;luben.tuikov@amd.com&gt;
Reviewed-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: move CS secure flag next the structs where it's used</title>
<updated>2020-04-28T20:20:29Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2019-11-27T20:55:35Z</published>
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<id>urn:sha1:4baa8ff0690e464443594353d63c989f0ed9f831</id>
<content type='text'>
So it's not mixed up with the CTX stuff.

Reviewed-by: Zhan Liu &lt;zhan.liu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add UAPI to create secure commands (v3)</title>
<updated>2020-04-28T20:20:28Z</updated>
<author>
<name>Luben Tuikov</name>
<email>luben.tuikov@amd.com</email>
</author>
<published>2019-09-23T23:02:41Z</published>
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<id>urn:sha1:e90c2b210bad457aab73d3357465afe4d4475f7e</id>
<content type='text'>
Add a flag to the command submission IOCTL
structure which when present indicates that this
command submission should be treated as
secure. The kernel driver uses this flag to
determine whether the engine should be
transitioned to secure or unsecure, or the work
can be submitted to a secure queue depending on
the IP.

v3: the flag is now at command submission IOCTL

Signed-off-by: Luben Tuikov &lt;luben.tuikov@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add UAPI for creating encrypted buffers</title>
<updated>2020-04-28T20:20:28Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2019-08-08T02:43:24Z</published>
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<id>urn:sha1:35ce006004821c5e9ae8fe03d048567cec99c41e</id>
<content type='text'>
Add a flag to the GEM_CREATE ioctl to create encrypted buffers.
Buffers with this flag set will be created with the TMZ bit set
in the PTEs or engines accessing them.  This is required in order
to properly access the data from the engines.

Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Huang Rui &lt;ray.huang@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add tiling flags from Mesa</title>
<updated>2020-04-28T15:50:46Z</updated>
<author>
<name>Marek Olšák</name>
<email>marek.olsak@amd.com</email>
</author>
<published>2020-04-18T00:50:30Z</published>
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<id>urn:sha1:c57053725d9bd7ab3e14fd0f8001714041df1280</id>
<content type='text'>
DCC_INDEPENDENT_128B is needed for displayble DCC on gfx10.
SCANOUT is not needed by the kernel, but Mesa uses it.

Signed-off-by: Marek Olšák &lt;marek.olsak@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Use better names to reflect it is CP MQD buffer</title>
<updated>2020-03-06T19:34:18Z</updated>
<author>
<name>Yong Zhao</name>
<email>Yong.Zhao@amd.com</email>
</author>
<published>2020-03-06T19:33:39Z</published>
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<id>urn:sha1:fa5bde8056cfb837a097785edb1e92f0985778ed</id>
<content type='text'>
Add "CP" to AMDGPU_GEM_CREATE_MQD_GFX9 to indicate it is only for CP MQD
buffer.

Signed-off-by: Yong Zhao &lt;Yong.Zhao@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add DMCUB to firmware query interface</title>
<updated>2019-11-13T20:29:42Z</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2019-10-25T18:15:08Z</published>
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<id>urn:sha1:976e51a7c0827a870fa08df6ee0a74e937ebbbd9</id>
<content type='text'>
The DMCUB firmware version can be read using the AMDGPU_INFO ioctl
or the amdgpu_firmware_info debugfs entry.

Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Reviewed-by: Hersen Wu &lt;hersenxs.wu@amd.com&gt;
Acked-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
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