<feed xmlns='http://www.w3.org/2005/Atom'>
<title>user/sven/linux.git/include/uapi/drm/amdgpu_drm.h, branch v5.5.14</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v5.5.14</id>
<link rel='self' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v5.5.14'/>
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<updated>2019-10-03T14:11:05Z</updated>
<entry>
<title>drm/amdgpu: return tcc_disabled_mask to userspace</title>
<updated>2019-10-03T14:11:05Z</updated>
<author>
<name>Marek Olšák</name>
<email>marek.olsak@amd.com</email>
</author>
<published>2019-09-24T21:53:25Z</published>
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<id>urn:sha1:cf21e76a6005016474623a375ae2e90364a02168</id>
<content type='text'>
UMDs need this for correct programming of harvested chips.

Signed-off-by: Marek Olšák &lt;marek.olsak@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Extends amdgpu vm definitions (v2)</title>
<updated>2019-09-13T22:35:32Z</updated>
<author>
<name>Oak Zeng</name>
<email>Oak.Zeng@amd.com</email>
</author>
<published>2019-07-26T20:57:50Z</published>
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<id>urn:sha1:484deaedfa03fa0d10e0b1ad3facc910ccc951a8</id>
<content type='text'>
Add RW mtype introduced for arcturus.

v2:
* Don't add probe-invalidation bit from UAPI
* Don't add unused AMDGPU_MTYPE_ definitions

Signed-off-by: Oak Zeng &lt;Oak.Zeng@amd.com&gt;
Signed-off-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Shaoyun Liu &lt;Shaoyun.Liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add flag to wipe VRAM on release</title>
<updated>2019-08-02T15:18:23Z</updated>
<author>
<name>Felix Kuehling</name>
<email>Felix.Kuehling@amd.com</email>
</author>
<published>2019-07-09T00:09:21Z</published>
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<id>urn:sha1:d8f4981e2e8a968411105db568f3d48256b2ebbc</id>
<content type='text'>
This memory allocation flag will be used to indicate BOs containing
sensitive data that should not be leaked to other processes.

Signed-off-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: extend AMDGPU_CTX_PRIORITY_NORMAL comment</title>
<updated>2019-07-16T18:08:30Z</updated>
<author>
<name>Emil Velikov</name>
<email>emil.velikov@collabora.com</email>
</author>
<published>2019-06-14T17:33:35Z</published>
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<id>urn:sha1:cf034477321e8c88d667514923763b93a0892f49</id>
<content type='text'>
Currently the AMDGPU_CTX_PRIORITY_* defines are used in both
drm_amdgpu_ctx_in::priority and drm_amdgpu_sched_in::priority.

Extend the comment to mention the CAP_SYS_NICE or DRM_MASTER requirement
is only applicable with the former.

Cc: Bas Nieuwenhuizen &lt;bas@basnieuwenhuizen.nl&gt;
Cc: Christian König &lt;christian.koenig@amd.com&gt;
Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Emil Velikov &lt;emil.velikov@collabora.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add pa_sc_tile_steering_override to drm_amdgpu_info_device</title>
<updated>2019-06-21T23:58:21Z</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2018-06-12T10:30:04Z</published>
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<id>urn:sha1:22e96fa62ec66ca9d21a76b74601fc200908fec3</id>
<content type='text'>
the initial/default value of pa_sc_tile_steering_override need to
be exposed to user mode driver

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add GDDR6 vram type</title>
<updated>2019-06-21T02:14:42Z</updated>
<author>
<name>Huang Rui</name>
<email>ray.huang@amd.com</email>
</author>
<published>2017-07-18T10:59:24Z</published>
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<id>urn:sha1:d67383e6b764957b39667af2754920e38a5eb43e</id>
<content type='text'>
New vram type.

Signed-off-by: Huang Rui &lt;ray.huang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add NV series gpu family id</title>
<updated>2019-06-20T20:54:58Z</updated>
<author>
<name>Huang Rui</name>
<email>ray.huang@amd.com</email>
</author>
<published>2017-07-19T01:43:26Z</published>
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<id>urn:sha1:107c34bcbf4737b457ca44156aa11e788cbb6b83</id>
<content type='text'>
Signed-off-by: Huang Rui &lt;ray.huang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add timeline support in amdgpu CS v3</title>
<updated>2019-04-12T16:27:57Z</updated>
<author>
<name>Chunming Zhou</name>
<email>david1.zhou@amd.com</email>
</author>
<published>2019-04-01T09:51:00Z</published>
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<id>urn:sha1:2624dd154bcc53ac2de16ecae9746ba867b6ca70</id>
<content type='text'>
syncobj wait/signal operation is appending in command submission.
v2: separate to two kinds in/out_deps functions
v3: fix checking for timeline syncobj

Signed-off-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Cc: Tobias Hector &lt;Tobias.Hector@amd.com&gt;
Cc: Jason Ekstrand &lt;jason@jlekstrand.net&gt;
Cc: Dave Airlie &lt;airlied@redhat.com&gt;
Cc: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
Cc: Lionel Landwerlin &lt;lionel.g.landwerlin@intel.com&gt;
Reviewed-by: Lionel Landwerlin &lt;lionel.g.landwerlin@intel.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add ioctl query for enabled ras features (v2)</title>
<updated>2019-03-19T20:36:51Z</updated>
<author>
<name>xinhui pan</name>
<email>xinhui.pan@amd.com</email>
</author>
<published>2018-12-17T07:09:07Z</published>
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<id>urn:sha1:5cb771143ed9552c672b6e1d6a3005a435b54e44</id>
<content type='text'>
Add a query for userspace to check which RAS features
are enabled.

v2: squash in warning fix

Signed-off-by: xinhui pan &lt;xinhui.pan@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add a new flag to AMDGPU_CTX_OP_QUERY_STATE2</title>
<updated>2019-03-19T20:36:51Z</updated>
<author>
<name>xinhui pan</name>
<email>xinhui.pan@amd.com</email>
</author>
<published>2018-12-17T06:31:12Z</published>
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<id>urn:sha1:ae363a212b145a0d4e0507e26e6c1b937181ec34</id>
<content type='text'>
Add AMDGPU_CTX_QUERY2_FLAGS_RAS_CE/UE which indicate if any error happened
between previous query and this query.

Signed-off-by: xinhui pan &lt;xinhui.pan@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
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