<feed xmlns='http://www.w3.org/2005/Atom'>
<title>user/sven/linux.git/include/uapi/drm, branch v5.17.1</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v5.17.1</id>
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<updated>2021-12-23T01:55:28Z</updated>
<entry>
<title>Merge tag 'amd-drm-next-5.17-2021-12-16' of https://gitlab.freedesktop.org/agd5f/linux into drm-next</title>
<updated>2021-12-23T01:55:28Z</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2021-12-23T01:55:28Z</published>
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<id>urn:sha1:b06103b5325364e0b9944024db41b400b9028df9</id>
<content type='text'>
amdgpu:
- Add some display debugfs entries
- RAS fixes
- SR-IOV fixes
- W=1 fixes
- Documentation fixes
- IH timestamp fix
- Misc power fixes
- IP discovery fixes
- Large driver documentation updates
- Multi-GPU memory use reductions
- Misc display fixes and cleanups
- Add new SMU debug option

amdkfd:
- SVM fixes

radeon:
- Fix typo in comment

From: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20211216202731.5900-1-alexander.deucher@amd.com
</content>
</entry>
<entry>
<title>Merge drm/drm-next into drm-misc-next</title>
<updated>2021-12-16T13:48:27Z</updated>
<author>
<name>Thomas Zimmermann</name>
<email>tzimmermann@suse.de</email>
</author>
<published>2021-12-16T13:47:38Z</published>
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<id>urn:sha1:9758ff2fa240173e9a45613b07774b7a78b7653e</id>
<content type='text'>
Backmerging for v5.16-rc5. Resolves a conflict between drm-misc-next
and drm-misc-fixes in the vc4 driver.

Signed-off-by: Thomas Zimmermann &lt;tzimmermann@suse.de&gt;
</content>
</entry>
<entry>
<title>drm/fourcc: Add packed 10bit YUV 4:2:0 format</title>
<updated>2021-12-16T10:23:22Z</updated>
<author>
<name>Dave Stevenson</name>
<email>dave.stevenson@raspberrypi.com</email>
</author>
<published>2021-12-15T09:17:37Z</published>
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<id>urn:sha1:006ea1b5822f9019bd722ffc6242bc0880879e3d</id>
<content type='text'>
Adds a format that is 3 10bit YUV 4:2:0 samples packed into
a 32bit word (with 2 spare bits).

Supported on Broadcom BCM2711 chips.

Signed-off-by: Dave Stevenson &lt;dave.stevenson@raspberrypi.com&gt;
Signed-off-by: Maxime Ripard &lt;maxime@cerno.tech&gt;
Acked-by: Thomas Zimmermann &lt;tzimmermann@suse.de&gt;
Link: https://lore.kernel.org/r/20211215091739.135042-2-maxime@cerno.tech
</content>
</entry>
<entry>
<title>amdgpu: fix some comment typos</title>
<updated>2021-12-14T21:10:58Z</updated>
<author>
<name>Yann Dirson</name>
<email>ydirson@free.fr</email>
</author>
<published>2021-12-13T23:30:30Z</published>
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<id>urn:sha1:326db0dc00e57432b689349b4da3e86c90d5d61a</id>
<content type='text'>
Signed-off-by: Yann Dirson &lt;ydirson@free.fr&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm: document DRM_IOCTL_MODE_GETFB2</title>
<updated>2021-12-14T11:03:32Z</updated>
<author>
<name>Simon Ser</name>
<email>contact@emersion.fr</email>
</author>
<published>2021-11-23T11:24:04Z</published>
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<id>urn:sha1:43d5ac7d07023cd133b978de473b3400edad941f</id>
<content type='text'>
There are a few details specific to the GETFB2 IOCTL.

It's not immediately clear how user-space should check for the
number of planes. Suggest using the handles field or the pitches
field.

The modifier array is filled with zeroes, ie. DRM_FORMAT_MOD_LINEAR.
So explicitly tell user-space to not look at it unless the flag is
set.

Changes in v2 (Daniel):
- Mention that handles should be used to compute the number of planes,
  and only refer to pitches as a fallback.
- Reword bit about undefined modifier.

Signed-off-by: Simon Ser &lt;contact@emersion.fr&gt;
Acked-by: Daniel Vetter &lt;daniel@ffwll.ch&gt;
Acked-by: Pekka Paalanen &lt;pekka.paalanen@collabora.com&gt;
Acked-by: Daniel Stone &lt;daniels@collabora.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20211123112400.22245-1-contact@emersion.fr
</content>
</entry>
<entry>
<title>drm/vmwgfx: Allow checking for gl43 contexts</title>
<updated>2021-12-09T18:16:29Z</updated>
<author>
<name>Zack Rusin</name>
<email>zackr@vmware.com</email>
</author>
<published>2021-12-06T17:26:17Z</published>
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<id>urn:sha1:abaad3d95b5117a17886d37cf0228712801cd259</id>
<content type='text'>
To make sure we're running on top of hardware that can support
GL4.3 we need to add a way of querying for those capabilities.
DRM_VMW_PARAM_GL43 allows userspace to check for presence of
GL4.3 capable contexts.

Signed-off-by: Zack Rusin &lt;zackr@vmware.com&gt;
Reviewed-by: Charmaine Lee &lt;charmainel@vmware.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20211206172620.3139754-10-zack@kde.org
</content>
</entry>
<entry>
<title>drm/virtgpu api: define a dummy fence signaled event</title>
<updated>2021-11-29T10:46:32Z</updated>
<author>
<name>Gurchetan Singh</name>
<email>gurchetansingh@chromium.org</email>
</author>
<published>2021-11-22T23:22:09Z</published>
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<id>urn:sha1:7e78781df491e4beb475bac22e6c44236a5002d7</id>
<content type='text'>
The current virtgpu implementation of poll(..) drops events
when VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK is enabled (otherwise
it's like a normal DRM driver).

This is because paravirtualized userspaces receives responses in a
buffer of type BLOB_MEM_GUEST, not by read(..).

To be in line with other DRM drivers and avoid specialized behavior,
it is possible to define a dummy event for virtgpu.  Paravirtualized
userspace will now have to call read(..) on the DRM fd to receive the
dummy event.

Fixes: b10790434cf2 ("drm/virtgpu api: create context init feature")
Reported-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
Signed-off-by: Gurchetan Singh &lt;gurchetansingh@chromium.org&gt;
Reviewed-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
Link: http://patchwork.freedesktop.org/patch/msgid/20211122232210.602-2-gurchetansingh@google.com
Signed-off-by: Gerd Hoffmann &lt;kraxel@redhat.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'drm-next-2021-11-03' of git://anongit.freedesktop.org/drm/drm</title>
<updated>2021-11-02T23:47:49Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2021-11-02T23:47:49Z</published>
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<id>urn:sha1:56d33754481fe0dc7436dc4ee4fbd44b3039361d</id>
<content type='text'>
Pull drm updates from Dave Airlie:
 "Summary below. i915 starts to add support for DG2 GPUs, enables DG1
  and ADL-S support by default, lots of work to enable DisplayPort 2.0
  across drivers. Lots of documentation updates and fixes across the
  board.

  core:
   - improve dma_fence, lease and resv documentation
   - shmem-helpers: allocate WC pages on x86, use vmf_insert_pin
   - sched fixes/improvements
   - allow empty drm leases
   - add dma resv iterator
   - add more DP 2.0 headers
   - DP MST helper improvements for DP2.0

  dma-buf:
   - avoid warnings, remove fence trace macros

  bridge:
   - new helper to get rid of panels
   - probe improvements for it66121
   - enable DSI EOTP for anx7625

  fbdev:
   - efifb: release runtime PM on destroy

  ttm:
   - kerneldoc switch
   - helper to clear all DMA mappings
   - pool shrinker optimizaton
   - remove ttm_tt_destroy_common
   - update ttm_move_memcpy for async use

  panel:
   - add new panel-edp driver

  amdgpu:
   - Initial DP 2.0 support
   - Initial USB4 DP tunnelling support
   - Aldebaran MCE support
   - Modifier support for DCC image stores for GFX 10.3
   - Display rework for better FP code handling
   - Yellow Carp/Cyan Skillfish updates
   - Cyan Skillfish display support
   - convert vega/navi to IP discovery asic enumeration
   - validate IP discovery table
   - RAS improvements
   - Lots of fixes

  i915:
   - DG1 PCI IDs + LMEM discovery/placement
   - DG1 GuC submission by default
   - ADL-S PCI IDs updated + enabled by default
   - ADL-P (XE_LPD) fixed and updates
   - DG2 display fixes
   - PXP protected object support for Gen12 integrated
   - expose multi-LRC submission interface for GuC
   - export logical engine instance to user
   - Disable engine bonding on Gen12+
   - PSR cleanup
   - PSR2 selective fetch by default
   - DP 2.0 prep work
   - VESA vendor block + MSO use of it
   - FBC refactor
   - try again to fix fast-narrow vs slow-wide eDP training
   - use THP when IOMMU enabled
   - LMEM backup/restore for suspend/resume
   - locking simplification
   - GuC major reworking
   - async flip VT-D workaround changes
   - DP link training improvements
   - misc display refactorings

  bochs:
   - new PCI ID

  rcar-du:
   - Non-contiguious buffer import support for rcar-du
   - r8a779a0 support prep

  omapdrm:
   - COMPILE_TEST fixes

  sti:
   - COMPILE_TEST fixes

  msm:
   - fence ordering improvements
   - eDP support in DP sub-driver
   - dpu irq handling cleanup
   - CRC support for making igt happy
   - NO_CONNECTOR bridge support
   - dsi: 14nm phy support for msm8953
   - mdp5: msm8x53, sdm450, sdm632 support

  stm:
   - layer alpha + zpo support

  v3d:
   - fix Vulkan CTS failure
   - support multiple sync objects

  gud:
   - add R8/RGB332/RGB888 pixel formats

  vc4:
   - convert to new bridge helpers

  vgem:
   - use shmem helpers

  virtio:
   - support mapping exported vram

  zte:
   - remove obsolete driver

  rockchip:
   - use bridge attach no connector for LVDS/RGB"

* tag 'drm-next-2021-11-03' of git://anongit.freedesktop.org/drm/drm: (1259 commits)
  drm/amdgpu/gmc6: fix DMA mask from 44 to 40 bits
  drm/amd/display: MST support for DPIA
  drm/amdgpu: Fix even more out of bound writes from debugfs
  drm/amdgpu/discovery: add SDMA IP instance info for soc15 parts
  drm/amdgpu/discovery: add UVD/VCN IP instance info for soc15 parts
  drm/amdgpu/UAPI: rearrange header to better align related items
  drm/amd/display: Enable dpia in dmub only for DCN31 B0
  drm/amd/display: Fix USB4 hot plug crash issue
  drm/amd/display: Fix deadlock when falling back to v2 from v3
  drm/amd/display: Fallback to clocks which meet requested voltage on DCN31
  drm/amd/display: move FPU associated DCN301 code to DML folder
  drm/amd/display: fix link training regression for 1 or 2 lane
  drm/amd/display: add two lane settings training options
  drm/amd/display: decouple hw_lane_settings from dpcd_lane_settings
  drm/amd/display: implement decide lane settings
  drm/amd/display: adopt DP2.0 LT SCR revision 8
  drm/amd/display: FEC configuration for dpia links in MST mode
  drm/amd/display: FEC configuration for dpia links
  drm/amd/display: Add workaround flag for EDID read on certain docks
  drm/amd/display: Set phy_mux_sel bit in dmub scratch register
  ...
</content>
</entry>
<entry>
<title>drm/amdgpu/UAPI: rearrange header to better align related items</title>
<updated>2021-10-28T18:26:59Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2021-10-25T19:06:34Z</published>
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<id>urn:sha1:72f4c9d57082cdd4054b599b3387220efd944095</id>
<content type='text'>
Move the RAS query parameters to align with the INFO query where
they are used.  No functional change.

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Luben Tuikov &lt;luben.tuikov@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm: Add R10 and R12 FourCC</title>
<updated>2021-10-28T07:20:45Z</updated>
<author>
<name>Laurent Pinchart</name>
<email>laurent.pinchart@ideasonboard.com</email>
</author>
<published>2021-10-27T23:31:40Z</published>
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<id>urn:sha1:31fa8cbce4664946a1688898410fee41ad05364d</id>
<content type='text'>
Add FourCCs for 10- and 12-bit red formats with padding to 16 bits.
They correspond to the V4L2 10- and 12-bit greyscale (V4L2_PIX_FMT_Y10
and V4L2_PIX_FMT_Y12) formats, as well as the Bayer formats with the
same bit depth (V4L2_PIX_FMT_SBGGR{10,12} and all other Bayer pattern
permutations).

These formats are not used by any kernel driver at this point, but need
to be exposed to applications by libcamera, which uses DRM FourCCs for
pixel formats.

Signed-off-by: Laurent Pinchart &lt;laurent.pinchart@ideasonboard.com&gt;
Signed-off-by: Dave Airlie &lt;airlied@redhat.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20211027233140.12268-1-laurent.pinchart@ideasonboard.com
</content>
</entry>
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