<feed xmlns='http://www.w3.org/2005/Atom'>
<title>user/sven/linux.git/include/uapi/drm, branch v6.12.46</title>
<subtitle>Linux Kernel
</subtitle>
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<updated>2025-08-15T10:13:39Z</updated>
<entry>
<title>drm/panthor: Add missing explicit padding in drm_panthor_gpu_info</title>
<updated>2025-08-15T10:13:39Z</updated>
<author>
<name>Boris Brezillon</name>
<email>boris.brezillon@collabora.com</email>
</author>
<published>2025-06-06T08:09:31Z</published>
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<id>urn:sha1:66d64d42d297c07c0f06ade62446267d929ad9f7</id>
<content type='text'>
[ Upstream commit 95cbab48782bf62e4093837dc15ac6133902c12f ]

drm_panthor_gpu_info::shader_present is currently automatically offset
by 4 byte to meet Arm's 32-bit/64-bit field alignment rules, but those
constraints don't stand on 32-bit x86 and cause a mismatch when running
an x86 binary in a user emulated environment like FEX. It's also
generally agreed that uAPIs should explicitly pad their struct fields,
which we originally intended to do, but a mistake slipped through during
the submission process, leading drm_panthor_gpu_info::shader_present to
be misaligned.

This uAPI change doesn't break any of the existing users of panthor
which are either arm32 or arm64 where the 64-bit alignment of
u64 fields is already enforced a the compiler level.

Changes in v2:
- Rename the garbage field into pad0 and adjust the comment accordingly
- Add Liviu's A-b

Changes in v3:
- Add R-bs

Fixes: 0f25e493a246 ("drm/panthor: Add uAPI")
Acked-by: Liviu Dudau &lt;liviu.dudau@arm.com&gt;
Reviewed-by: Adrián Larumbe &lt;adrian.larumbe@collabora.com&gt;
Reviewed-by: Steven Price &lt;steven.price@arm.com&gt;
Link: https://lore.kernel.org/r/20250606080932.4140010-2-boris.brezillon@collabora.com
Signed-off-by: Boris Brezillon &lt;boris.brezillon@collabora.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>accel/ivpu: Remove copy engine support</title>
<updated>2025-07-06T09:01:37Z</updated>
<author>
<name>Andrzej Kacprowski</name>
<email>Andrzej.Kacprowski@intel.com</email>
</author>
<published>2024-10-17T14:58:09Z</published>
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<id>urn:sha1:0c3fa6e8441b1e1d18923fa121ea5f6f1793cf08</id>
<content type='text'>
[ Upstream commit 94b2a2c0e7cba3f163609dbd94120ee533ad2a07 ]

Copy engine was deprecated by the FW and is no longer supported.
Compute engine includes all copy engine functionality and should be used
instead.

This change does not affect user space as the copy engine was never
used outside of a couple of tests.

Signed-off-by: Andrzej Kacprowski &lt;Andrzej.Kacprowski@intel.com&gt;
Reviewed-by: Jacek Lawrynowicz &lt;jacek.lawrynowicz@linux.intel.com&gt;
Reviewed-by: Jeffrey Hugo &lt;quic_jhugo@quicinc.com&gt;
Signed-off-by: Jacek Lawrynowicz &lt;jacek.lawrynowicz@linux.intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20241017145817.121590-4-jacek.lawrynowicz@linux.intel.com
Stable-dep-of: a47e36dc5d90 ("accel/ivpu: Trigger device recovery on engine reset/resume failure")
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>accel/ivpu: Fix the NPU's DPU frequency calculation</title>
<updated>2025-05-02T05:58:56Z</updated>
<author>
<name>Andrzej Kacprowski</name>
<email>Andrzej.Kacprowski@intel.com</email>
</author>
<published>2025-04-01T15:59:11Z</published>
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<id>urn:sha1:60cb4dfcf7390f8a61fbb2880bed33bf6b03bd67</id>
<content type='text'>
[ Upstream commit 6c2b75404d33caa46a582f2791a70f92232adb71 ]

Fix the frequency returned to the user space by
the DRM_IVPU_PARAM_CORE_CLOCK_RATE GET_PARAM IOCTL.
The kernel driver returned CPU frequency for MTL and bare
PLL frequency for LNL - this was inconsistent and incorrect
for both platforms. With this fix the driver returns maximum
frequency of the NPU data processing unit (DPU) for all HW
generations. This is what user space always expected.

Also do not set CPU frequency in boot params - the firmware
does not use frequency passed from the driver, it was only
used by the early pre-production firmware.
With that we can remove CPU frequency calculation code.

Show NPU frequency in FREQ_CHANGE interrupt when frequency
tracking is enabled.

Fixes: 8a27ad81f7d3 ("accel/ivpu: Split IP and buttress code")
Cc: stable@vger.kernel.org # v6.11+
Signed-off-by: Andrzej Kacprowski &lt;Andrzej.Kacprowski@intel.com&gt;
Signed-off-by: Maciej Falkowski &lt;maciej.falkowski@linux.intel.com&gt;
Reviewed-by: Jeff Hugo &lt;jeff.hugo@oss.qualcomm.com&gt;
Signed-off-by: Jacek Lawrynowicz &lt;jacek.lawrynowicz@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20250401155912.4049340-2-maciej.falkowski@linux.intel.com
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/xe/oa/uapi: Define and parse OA sync properties</title>
<updated>2025-02-27T12:30:13Z</updated>
<author>
<name>Ashutosh Dixit</name>
<email>ashutosh.dixit@intel.com</email>
</author>
<published>2024-10-22T20:03:47Z</published>
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<id>urn:sha1:803d418b73387fda392ddd83eace757ac25cf15d</id>
<content type='text'>
[ Upstream commit c8507a25cebd179db935dd266a33c51bef1b1e80 ]

Now that we have laid the groundwork, introduce OA sync properties in the
uapi and parse the input xe_sync array as is done elsewhere in the
driver. Also add DRM_XE_OA_CAPS_SYNCS bit in OA capabilities for userspace.

v2: Fix and document DRM_XE_SYNC_TYPE_USER_FENCE for OA (Matt B)
    Add DRM_XE_OA_CAPS_SYNCS bit to OA capabilities (Jose)

Acked-by: José Roberto de Souza &lt;jose.souza@intel.com&gt;
Reviewed-by: Jonathan Cavitt &lt;jonathan.cavitt@intel.com&gt;
Signed-off-by: Ashutosh Dixit &lt;ashutosh.dixit@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20241022200352.1192560-3-ashutosh.dixit@intel.com
Stable-dep-of: f0ed39830e60 ("xe/oa: Fix query mode of operation for OAR/OAC")
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add a BO metadata flag to disable write compression for Vulkan</title>
<updated>2025-02-17T09:05:09Z</updated>
<author>
<name>Marek Olšák</name>
<email>marek.olsak@amd.com</email>
</author>
<published>2025-01-24T14:43:45Z</published>
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<id>urn:sha1:20a57f68db1b7e8de97acd1f04bb697f3c6ad589</id>
<content type='text'>
commit 2255b40cacc2e5ef1b127770fc1808c60de4a2fc upstream.

Vulkan can't support DCC and Z/S compression on GFX12 without
WRITE_COMPRESS_DISABLE in this commit or a completely different DCC
interface.

AMDGPU_TILING_GFX12_SCANOUT is added because it's already used by userspace.

Cc: stable@vger.kernel.org # 6.12.x
Signed-off-by: Marek Olšák &lt;marek.olsak@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>drm/xe/ptl: L3bank mask is not available on the media GT</title>
<updated>2024-12-14T19:03:44Z</updated>
<author>
<name>Shekhar Chauhan</name>
<email>shekhar.chauhan@intel.com</email>
</author>
<published>2024-10-07T15:41:44Z</published>
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<id>urn:sha1:43a859bd40ce3478fd7652285d1f27bc062b2ea0</id>
<content type='text'>
[ Upstream commit 9ab440a9d0426cf7842240891cc457155db1a97e ]

On PTL platforms with media version 30.00, the fuse registers for
reporting L3 bank availability to the GT just read out as ~0 and do not
provide proper values.  Xe does not use the L3 bank mask for anything
internally; it only passes the mask through to userspace via the GT
topology query.

Since we don't have any way to get the real L3 bank mask, we don't want
to pass garbage to userspace.  Passing a zeroed mask or a copy of the
primary GT's L3 bank mask would also be inaccurate and likely to cause
confusion for userspace.  The best approach is to simply not include L3
in the list of masks returned by the topology query in cases where we
aren't able to provide a meaningful value.  This won't change the
behavior for any existing platforms (where we can always obtain L3 masks
successfully for all GTs), it will only prevent us from mis-reporting
bad information on upcoming platform(s).

There's a good chance this will become a formal workaround in the
future, but for now we don't have a lineage number so "no_media_l3" is
used in place of a lineage as the OOB workaround descriptor.

v2:
 - Re-calculate query size to properly match data returned. (Gustavo)
 - Update kerneldoc to clarify that the L3bank mask may not be included
   in the query results if the hardware doesn't make it available.
   (Gustavo)

Cc: Matt Atwood &lt;matthew.s.atwood@intel.com&gt;
Cc: Gustavo Sousa &lt;gustavo.sousa@intel.com&gt;
Signed-off-by: Shekhar Chauhan &lt;shekhar.chauhan@intel.com&gt;
Co-developed-by: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Signed-off-by: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Reviewed-by: Jonathan Cavitt &lt;jonathan.cavitt@intel.com&gt;
Reviewed-by: Gustavo Sousa &lt;gustavo.sousa@intel.com&gt;
Acked-by: Francois Dugast &lt;francois.dugast@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20241007154143.2021124-2-matthew.d.roper@intel.com
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>Merge v6.11-rc7 into drm-next</title>
<updated>2024-09-11T07:18:15Z</updated>
<author>
<name>Simona Vetter</name>
<email>simona.vetter@ffwll.ch</email>
</author>
<published>2024-09-11T07:18:15Z</published>
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<id>urn:sha1:b615b9c36cae0468491547206406a909a9a37f26</id>
<content type='text'>
Thomas needs 5a498d4d06d6 ("drm/fbdev-dma: Only install deferred I/O
if necessary") in drm-misc, so start the backmerge cascade.

Signed-off-by: Simona Vetter &lt;simona.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>Merge tag 'drm-misc-fixes-2024-09-05' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-fixes</title>
<updated>2024-09-06T01:25:46Z</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2024-09-06T01:25:38Z</published>
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<id>urn:sha1:ca10367a5abe5f04df1374b227a10439ef686b90</id>
<content type='text'>
A zpos normalization fix for komeda, a register bitmask fix for nouveau,
a memory leak fix for imagination, three fixes for the recent bridge
HDMI work, a potential DoS fix and a cache coherency for panthor, a
change of panel compatible and a deferred-io fix when used with
non-highmem memory.

Signed-off-by: Dave Airlie &lt;airlied@redhat.com&gt;

From: Maxime Ripard &lt;mripard@redhat.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20240905-original-radical-guan-e7a2ae@houat
</content>
</entry>
<entry>
<title>drm/panthor: Restrict high priorities on group_create</title>
<updated>2024-09-05T07:33:33Z</updated>
<author>
<name>Mary Guillemard</name>
<email>mary.guillemard@collabora.com</email>
</author>
<published>2024-09-03T14:49:55Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=5f7762042f8a5377bd8a32844db353c0311a7369'/>
<id>urn:sha1:5f7762042f8a5377bd8a32844db353c0311a7369</id>
<content type='text'>
We were allowing any users to create a high priority group without any
permission checks. As a result, this was allowing possible denial of
service.

We now only allow the DRM master or users with the CAP_SYS_NICE
capability to set higher priorities than PANTHOR_GROUP_PRIORITY_MEDIUM.

As the sole user of that uAPI lives in Mesa and hardcode a value of
MEDIUM [1], this should be safe to do.

Additionally, as those checks are performed at the ioctl level,
panthor_group_create now only check for priority level validity.

[1]https://gitlab.freedesktop.org/mesa/mesa/-/blob/f390835074bdf162a63deb0311d1a6de527f9f89/src/gallium/drivers/panfrost/pan_csf.c#L1038

Signed-off-by: Mary Guillemard &lt;mary.guillemard@collabora.com&gt;
Fixes: de8548813824 ("drm/panthor: Add the scheduler logical block")
Cc: stable@vger.kernel.org
Reviewed-by: Boris Brezillon &lt;boris.brezillon@collabora.com&gt;
Signed-off-by: Boris Brezillon &lt;boris.brezillon@collabora.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20240903144955.144278-2-mary.guillemard@collabora.com
</content>
</entry>
<entry>
<title>drm/msm: Expose expanded UBWC config uapi</title>
<updated>2024-08-30T17:41:19Z</updated>
<author>
<name>Connor Abbott</name>
<email>cwabbott0@gmail.com</email>
</author>
<published>2024-08-07T13:04:58Z</published>
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<id>urn:sha1:d7eafed3223af19add14b67a390ec2b983d890e0</id>
<content type='text'>
This adds extra parameters that affect UBWC tiling that will be used by
the Mesa implementation of VK_EXT_host_image_copy.

Signed-off-by: Connor Abbott &lt;cwabbott0@gmail.com&gt;
Patchwork: https://patchwork.freedesktop.org/patch/607401/
Signed-off-by: Rob Clark &lt;robdclark@chromium.org&gt;
</content>
</entry>
</feed>
