<feed xmlns='http://www.w3.org/2005/Atom'>
<title>user/sven/linux.git/include/uapi/linux/kfd_ioctl.h, branch v5.4.43</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v5.4.43</id>
<link rel='self' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v5.4.43'/>
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<updated>2019-08-07T15:21:38Z</updated>
<entry>
<title>Revert "drm/amdkfd: New IOCTL to allocate queue GWS"</title>
<updated>2019-08-07T15:21:38Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2019-08-07T05:23:07Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=4b3e30ed3ec7864e798403a63ff2e96bd0c19ab0'/>
<id>urn:sha1:4b3e30ed3ec7864e798403a63ff2e96bd0c19ab0</id>
<content type='text'>
This reverts commit 1a058c3376765ee31d65e28cbbb9d4ff15120056.

This interface is still in too much flux.  Revert until
it's sorted out.

Acked-by: Oak Zeng &lt;Oak.Zeng@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: New IOCTL to allocate queue GWS</title>
<updated>2019-05-28T19:44:31Z</updated>
<author>
<name>Oak Zeng</name>
<email>Oak.Zeng@amd.com</email>
</author>
<published>2019-05-07T03:11:14Z</published>
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<id>urn:sha1:1a058c3376765ee31d65e28cbbb9d4ff15120056</id>
<content type='text'>
Add a new kfd ioctl to allocate queue GWS. Queue
GWS is released on queue destroy.

Signed-off-by: Oak Zeng &lt;Oak.Zeng@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: Introduce XGMI SDMA queue type</title>
<updated>2019-05-24T17:21:02Z</updated>
<author>
<name>Oak Zeng</name>
<email>Oak.Zeng@amd.com</email>
</author>
<published>2019-02-07T20:02:27Z</published>
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<id>urn:sha1:1b4670f6983156526c286723465fdf805070b45d</id>
<content type='text'>
Existing QUEUE_TYPE_SDMA means PCIe optimized SDMA queues.
Introduce a new QUEUE_TYPE_SDMA_XGMI, which is optimized
for non-PCIe transfer such as XGMI.

Signed-off-by: Oak Zeng &lt;Oak.Zeng@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: Expose HDP registers to user space</title>
<updated>2019-05-24T17:20:47Z</updated>
<author>
<name>Oak Zeng</name>
<email>Oak.Zeng@amd.com</email>
</author>
<published>2019-04-11T19:43:39Z</published>
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<id>urn:sha1:d8e408a82704c86ba87c3d58cfe69dcdb758aa07</id>
<content type='text'>
Introduce a new memory type (KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) and
expose mmio page of HDP registers to user space through this new
memory type.

v2: moved remapped hdp regs to adev struct
v3: rename the new memory type to ALLOC_MEM_FLAGS_MMIO_REMAP
v4: use more generic function name
v5: Fail remapped mmio allocation for asics before gfx9

Signed-off-by: Oak Zeng &lt;Oak.Zeng@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;felix.kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Remap hdp coherency registers</title>
<updated>2019-05-24T17:20:47Z</updated>
<author>
<name>Oak Zeng</name>
<email>Oak.Zeng@amd.com</email>
</author>
<published>2019-04-04T20:47:34Z</published>
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<id>urn:sha1:88807dc8d573c0f718d0d26f592f212c5a487cf0</id>
<content type='text'>
Remap HDP_MEM_COHERENCY_FLUSH_CNTL and HDP_REG_COHERENCY_FLUSH_CNTL
to an empty page in mmio space. We will later map this page to process
space so application can flush hdp. This can't be done properly at
those registers' original location because it will expose more than
desired registers to process space.

v2: Use explicit register hole location
v3: Moved remapped hdp registers into adev struct
v4: Use more generic name for remapped page
    Expose register offset in kfd_ioctl.h
v5: Move hdp register remap function to nbio ip function
v6: Fixed operator precedence issue and other bugs

Signed-off-by: Oak Zeng &lt;Oak.Zeng@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: add RAS ECC event support (v3)</title>
<updated>2019-03-19T20:36:51Z</updated>
<author>
<name>Eric Huang</name>
<email>JinhuiEric.Huang@amd.com</email>
</author>
<published>2019-01-11T19:38:51Z</published>
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<id>urn:sha1:9b54d2017687df9fa827faf9e4022973b87fc0ff</id>
<content type='text'>
RAS ECC event will combine with GPU reset event, due to
ECC interrupts are caused by uncorrectable error that triggers
GPU reset.

v2: Fix misleading-indentation warning
v3: fix build with CONFIG_HSA_AMD disabled

Signed-off-by: Eric Huang &lt;JinhuiEric.Huang@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: Add DMABuf import functionality</title>
<updated>2018-12-07T23:13:54Z</updated>
<author>
<name>Felix Kuehling</name>
<email>Felix.Kuehling@amd.com</email>
</author>
<published>2018-11-21T02:00:29Z</published>
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<id>urn:sha1:1dde0ea95b782425b95455d487cb44991525a1d1</id>
<content type='text'>
This is used for interoperability between ROCm compute and graphics
APIs. It allows importing graphics driver BOs into the ROCm SVM
address space for zero-copy GPU access.

The API is split into two steps (query and import) to allow user mode
to manage the virtual address space allocation for the imported buffer.

Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>uapi: fix more linux/kfd_ioctl.h userspace compilation errors</title>
<updated>2018-11-05T20:46:51Z</updated>
<author>
<name>Dmitry V. Levin</name>
<email>ldv@altlinux.org</email>
</author>
<published>2018-11-01T11:03:28Z</published>
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<id>urn:sha1:8e7f91719db36440d63de37331367be9700ca0c7</id>
<content type='text'>
Consistently use types provided by &lt;linux/types.h&gt; via &lt;drm/drm.h&gt;
to fix struct kfd_ioctl_get_queue_wave_state_args userspace compilation errors.

Fixes: 5df099e8bc83f ("drm/amdkfd: Add wavefront context save state retrieval ioctl")
Signed-off-by: Dmitry V. Levin &lt;ldv@altlinux.org&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>uapi: fix linux/kfd_ioctl.h userspace compilation errors</title>
<updated>2018-11-05T20:46:35Z</updated>
<author>
<name>Dmitry V. Levin</name>
<email>ldv@altlinux.org</email>
</author>
<published>2018-11-01T11:03:08Z</published>
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<id>urn:sha1:aba118389a6fb2ad7958de0f37b5869852bd38cf</id>
<content type='text'>
Consistently use types provided by &lt;linux/types.h&gt; via &lt;drm/drm.h&gt;
to fix the following linux/kfd_ioctl.h userspace compilation errors:

/usr/include/linux/kfd_ioctl.h:250:2: error: unknown type name 'uint32_t'
  uint32_t reset_type;
/usr/include/linux/kfd_ioctl.h:251:2: error: unknown type name 'uint32_t'
  uint32_t reset_cause;
/usr/include/linux/kfd_ioctl.h:252:2: error: unknown type name 'uint32_t'
  uint32_t memory_lost;
/usr/include/linux/kfd_ioctl.h:253:2: error: unknown type name 'uint32_t'
  uint32_t gpu_id;

Fixes: 0c119abad7f0d ("drm/amd: Add kfd ioctl defines for hw_exception event")
Cc: &lt;stable@vger.kernel.org&gt; # v4.19
Signed-off-by: Dmitry V. Levin &lt;ldv@altlinux.org&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: Add wavefront context save state retrieval ioctl</title>
<updated>2018-09-27T02:09:15Z</updated>
<author>
<name>Jay Cornwall</name>
<email>Jay.Cornwall@amd.com</email>
</author>
<published>2017-05-02T22:39:37Z</published>
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<id>urn:sha1:5df099e8bc83f4f3af8711ee0b9b8faef359ffff</id>
<content type='text'>
Wavefront context save data is of interest to userspace clients for
debugging static wavefront state. The MQD contains two parameters
required to parse the control stack and the control stack itself
is kept in the MQD from gfx9 onwards.

Add an ioctl to fetch the context save area and control stack offsets
and to copy the control stack to a userspace address if it is kept in
the MQD.

Signed-off-by: Jay Cornwall &lt;Jay.Cornwall@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
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